Ultra-low Voltage: Is Your Slack Really Positive? Are You Sure?

Ultra-low Voltage: Is Your Slack Really Positive? Are You Sure?
by Paul McLellan on 08-06-2015 at 7:00 am

During synthesis and static timing the main figure of merit is “slack”. If a signal arrives with time to spare before it is needed (often measured against the setup time before a clock changes at a register) then the slack is positive. Positive slack is generally a good thing, although it can indicate over-design if … Read More


More FPGA-based prototype myths quashed

More FPGA-based prototype myths quashed
by Don Dingee on 08-03-2015 at 12:00 pm

Speaking of having the right tools, FPGA-based prototyping has become as much if not more about the synthesis software than it is about the FPGA hardware. This is a follow-up to my post earlier this month on FPGA-based prototyping, but with a different perspective from another vendor. Instead of thinking about what else can be done… Read More


Synflow and Cx

Synflow and Cx
by Paul McLellan on 03-04-2015 at 9:00 am

When hardware designers hear about a new language their heart sinks. We already have Verilog, SystemVerilog and VHDL. And if you go up a level, we have C, C++ and SystemC. Isn’t that enough? However, if you tell a software engineer about a new language they are interested, there are hundreds of programming language and hundreds… Read More


Dealing with FPGA IP in all its forms

Dealing with FPGA IP in all its forms
by Don Dingee on 02-12-2015 at 10:00 pm

One of the recurring themes I see here in the pages of SemiWiki and elsewhere is this pitched, bordering on religious battle between Altera and Xilinx. Just because both are FPGA technologies, the tendency is to put them in the same bucket, drawing direct comparisons between them. Some folks say there is no comparison; Xilinx has… Read More


Concept: From Schematics to Debug

Concept: From Schematics to Debug
by Paul McLellan on 02-05-2015 at 7:00 am

In the late 1990s I was the VP Engineering at Ambit Design Systems. We had a synthesis product (called BuildGates, nobody ever forgot the name). Both our own engineers and our customers wanted to be able to take a look at the gate-level netlist that was generated from their RTL. We used a product from a company called Concept Engineering… Read More


Designing Hardware with C++ and its Advantages

Designing Hardware with C++ and its Advantages
by Pawan Fangaria on 10-27-2014 at 10:00 am

Very recently, I was seeing intense discussions on the need for agile hardware development just like agile software and ideas were being sought from experts as well as individuals. While in software world it has already evolved, in hardware world it’s yet to see the shift in paradigm. My point is that the end goal of agile hardware… Read More


Designing the Right Architecture Using HLS

Designing the Right Architecture Using HLS
by Pawan Fangaria on 09-17-2014 at 9:05 am

With the advent of HLS tools, general notion which comes to mind is that okay, there’s an automated tool which can optimize your design description written in C++/SystemC and provide you a perfect RTL. In real life, it’s not so, any design description needs hardware designer’s expertise to adopt right algorithm and architecture… Read More


International Workshop on Logic and Synthesis

International Workshop on Logic and Synthesis
by Paul McLellan on 04-20-2014 at 12:54 am

There are always a number of other events that are colocated with DAC. One this year is the 23rd International Workshop on Logic and Synthesis (IWLS) that is held the weekend before DAC on May 30th and June 1st. Strictly speaking it is not colocated since it is in the Galleria Park Hotel on Sutter Street a few blocks away whereas DAC itself… Read More


Top 10 Reasons to Use Vivado Design Suite

Top 10 Reasons to Use Vivado Design Suite
by Paul McLellan on 03-23-2014 at 7:05 am

Here are the top 10 reasons to use the Xilinx Vivado Design Suite to design your All Programmable Devices:

Reason number 10: Accelerate verification by over 100XThe Vivado Design Suite System Edition lets you do design at the C, C++ or systemC level. But a side-benefit is that you can use these languages for verification at performances… Read More


Mentor Buys Oasys

Mentor Buys Oasys
by Paul McLellan on 12-14-2013 at 1:24 pm

Mentor is acquiring Oasys, subject to all the usual caveats about shareholder and regulatory approval. The shareholder paperwork went out earlier this week. The common stock is valueless so presumably the price is low (and Mentor historically has not paid high prices for its acquisitions).

So what is going to happen with the technology?… Read More