The advancements in deep submicron technology and adding multiple functionalities to reduce costs combined with scaling existing operations means that SoC designs become ever more complex. The biggest driving factors to go below the 16nm process node are the decrease in power and the increase in performance … Read More
This year is proving to be a momentous one for U.S. semiconductor manufacturing. During a global chip shortage and record inflation, President Biden signed into effect the CHIPS and Science Act – which so far is the greatest boon to U.S. semiconductor manufacturing in history, with $52 billion in subsidies for chip manufacturers… Read More
This webinar will introduce to you a revolutionary new way to do prototyping and emulation at best-in-class performance, productivity, and pricing by unifying the hardware and a new software stack so one system is capable of prototyping and delivering essential emulation functionality.
The speed of Moore’s law… Read More
We need more and more complex chips and SoCs for all new applications that use the latest technologies like AI. For example, Apple’s 5nm SoC A14 features 6-core CPU, 4 core-GPU and 16-core neural engine capable of 11 trillion operations per second, which incorporates 11.8 billion transistors, and AWS 7nm 64-bit Graviton2 custom… Read More
Dan is joined by Anupam Bakshi, founder and CEO of Agnisys. Anupam has more than two decades of experience implementing a wide range of products and services in the high tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology Inc., PictureTel, Blackstone,… Read More
For the past few decades, System-on-Chip (SoC) has been the gold standard for optimizing the performance and cost of electronic systems. Pulling together practically all of a smartphone’s digital and analog capabilities into a monolithic chip, the mobile application processor serves as a near-perfect example of an SoC. But… Read More
Typically, there is an existential rift between the on-chip access requirements for test and the need for security in SoCs. Using traditional deterministic scan techniques has meant opening up full read and write access to the flops in a design through the scan chains. Having this kind of access easily defeats the best designed… Read More
According to the ESD Alliance, the single biggest revenue category in our industry is for semiconductor IP, so the concept of IP reuse is firmly established as a way to get complex products to market more quickly and reducing risk. On the flip side, with hundreds or even thousands of IP blocks in a complex SoC, how does a team, division… Read More
The success of modern battery-powered products depends as much on useful operating time between charges as on functionality. FinFET process technologies overtook earlier planar CMOS in part because they significantly reduce leakage power. But they exacerbate dynamic power consumption thanks to increased pin capacitances.… Read More
Lauro Rizzatti recently interviewed Jean-Marie Brunet, vice president of product management and product engineering in the Scalable Verification Solution division at Siemens EDA, about why hardware-assisted verification is a must have for today’s semiconductor designs. A condensed version of their discussion is below.… Read More
