DVClub Europe – Performance Testing and Analysis

DVClub Europe – Performance Testing and Analysis
by Admin on 04-03-2023 at 3:51 pm

Performance Testing and Analysis

Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster, to interconnect to die-to-die.

Agenda (BST)

12:00 Welcome and Introduction – Mike Bartley, Tessolve

12:00 Nick Heaton, Cadence Design Systems – SoC Verification in a Multi-chip,Read More


Webinar: How Deep Data Analytics Accelerates SoC Time-to-Market by 6 Months

Webinar: How Deep Data Analytics Accelerates SoC Time-to-Market by 6 Months
by Admin on 04-03-2023 at 3:04 pm

SoCs have become very complex silicon solutions. They now consist of 100s of millions or billions of gates, 100 or more discrete Semiconductor Intellectual Property (SIP) blocks, megabytes of volatile and non-volatile embedded memory and multiple CPU cores.

Join us on Thursday, April 27 for this 30-minute webinar as we describe

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31st IFIP/IEEE International Conference on Very Large-Scale Integration (VLSI-SoC)

31st IFIP/IEEE International Conference on Very Large-Scale Integration (VLSI-SoC)
by Admin on 02-20-2023 at 8:49 pm

VLSI-SoC 2023 is the 31st  in a series of international conferences sponsored by the International Federation for Information Processing Technical Committee 10 Working Group 5, IEEE CEDA, and IEEE CASS, which explore the state-of-the-art in the areas of Very Large-Scale Integration (VLSI) and System-on-Chip (SoC) design.Read More


Speeding up Chiplet-Based Design Through Hardware Emulation

Speeding up Chiplet-Based Design Through Hardware Emulation
by Kalar Rajendiran on 02-16-2023 at 10:00 am

Barriers on the Continuum to SiP

The first chiplets focused summit took place last month. So many accomplished speakers gave keynote talks on what direction should and would the Chiplets ecosystem evolution take. Corigine presented the keynote on what direction hardware emulation should and would evolve for speeding up chiplet- based designs. During a pre-conference… Read More


Webinar: PCIe/CXL Latency and Power Considerations for HPC SoCs

Webinar: PCIe/CXL Latency and Power Considerations for HPC SoCs
by Admin on 12-15-2022 at 3:53 pm

*Company email required for registration*

If you are designing chips for high-performance computing (HPC) and data center applications, bandwidth is, of course, a key consideration. However, as data centers get bigger and the required compute power increases, keeping power consumption to a minimum becomes a priority. In

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Achieving 400W Thermal Envelope for AI Datacenter SoCs

Achieving 400W Thermal Envelope for AI Datacenter SoCs
by Kalar Rajendiran on 12-05-2022 at 10:00 am

Alchip BlockDiagram Oct 26 2022 tsmc na oip presentation

Successful ASIC providers offer top-notch infrastructure and methodologies that can accommodate varied demands from a multitude of customers. Such ASIC providers also need access to best-in-class IP portfolio, advanced packaging and test capabilities, and heterogeneous chiplet integration capability among other things.… Read More


Integrating High Speed IP at 5nm

Integrating High Speed IP at 5nm
by Pavan Patel on 11-10-2022 at 6:00 am

Figure 1

Introduction:

The advancements in deep submicron technology and adding multiple functionalities to reduce costs combined with scaling existing operations means that SoC designs become ever more complex. The biggest driving factors to go below the 16nm process node are the decrease in power and the increase in performance … Read More


Webinar: Code Review for System Architects

Webinar: Code Review for System Architects
by Admin on 11-02-2022 at 11:59 am

* Company email is required*

Register management tools have been used mostly in a bottom-up approach. There are some documents and/or spreadsheets created by the System Architects that are delivered to the design and verification teams. They then start capturing the HW/SW interface of the peripheral IPs in their in-house or

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