In the semiconductor design industry, most of the designs are created and optimized at the RTL level, mainly through home grown scripts or manual methods. As there can be several iterations in optimizing the hierarchy for physical implementation, it’s too late to do the hierarchical optimizations after reaching the floor plan… Read More
Tag: soc
IoT will depend on FPGAs
The IoT (Internet of Things) creates an ambivalence within me. Part of me hates computers and being connected, the other is currently working on a boiler controller that even adaptively predicts and senses when the next wood load is needed and alerts the wife. Yup pray for her. I really use FPGAs and CPLDs around the farm and I am slowly… Read More
NoCs for system-level power management
Most of the buzz on network-on-chip is around simplifying and scaling interconnect, especially in multicore SoCs where AMBA buses and crossbars run into issues as more and more cores enter a design. Designers may want to explore how NoCs can help with a more power-aware approach.… Read More
When is a Million-Year MTBF Too Short?
The reliability metric, Mean Time Between Failures (MTBF), is often misunderstood. Use of an MTBF metric generally assumes a random failure process, one that is very infrequent and has no memory of past failures. Such failure modes can occur in System-on-Chip (SoC) designs and include radiation effects, synchronizer malfunctions… Read More
Winds of Change in the Custom Chip Market
The most interesting part of the semiconductor market for me has always been the Custom Chip sector – the FPGA, ASIC and SoC companies where I have spent my entire career. These three segments provide an excellent barometer of the overall state of financial health and technological innovation for the entire High Tech industry, … Read More
S-engine Moves up the Integration of IPs into SoCs
As the semiconductor design community is seeing higher and higher levels of abstraction with standard IPs and other complex, customized IPs and sub-systems integrated together at the system level, sooner than later we will find SoCs to be just assemblies of numerous IPs selected off-the-self according to the design needs and… Read More
So Easy To Learn VIP Integration into UVM Environment
It goes without saying that VIPs really play a Very Important Part in SoC verification today. It has created a significant semiconductor market segment in the fabless world of SoC and IP design & verification. In order to meet the aggressive time-to-market for IPs and SoCs, it’s imperative that readymade VIPs which are proven… Read More
TSMC (TSM) is Having Another SoC Year!
TSMC’s stock has more than doubled in the last five years. Coincidentally that is when I started blogging about TSMC. QCOM stock has experienced a similar doubling during this time as have other TSMC customers. The question is: What is next for TSMC? As I have mentioned before, you would be better off taking stock tips from your dog… Read More
Synopsys Galaxy Platform & Lynx Design System supports FD-SOI
This is a new brick that Synopsys brings to build FD-SOI credibility. We have talked at Semiwiki about FD-SOI technology developed by the LETI and STM, and recently endorsed by Samsung Foundry, offering a more than credible second source to STM. And we have said that the FD-SOI introduction will need to be supported by EDA and IP vendors… Read More
Different Approaches to System Level Power Modeling and Analysis for Early Design Phases
At DATEthis year in Dresden, Bernhard Fischer from Siemens CT(Corporate Technology) has presented an interesting summary of the various techniques used for power modeling and analysis at the architectural level. He went through the pros and cons of using spreadsheets, timed virtual platforms annotated with power numbers … Read More