ASIC Days Are Here Again

ASIC Days Are Here Again
by Paul McLellan on 12-18-2014 at 7:00 am

Technology often goes in cycles. Thirty years ago the dominant mode of computing was a shared computing resource with comparatively dumb terminals. Think of a Vax accessed by terminals. Then workstations and the PC came along and the dominant mode became a computer on everyone’s desk. Then the smartphone came along and … Read More


Expert Tool to Easily Debug RTL and Reuse in SoCs

Expert Tool to Easily Debug RTL and Reuse in SoCs
by Pawan Fangaria on 12-16-2014 at 7:00 pm

SoC design these days has become a complex and tricky phenomenon involving integration of multiple IPs and legacy RTL code which could be in different languages, sourced from various third parties across the globe. Understanding and reusing RTL code is imperative in SoC integration which needs capable tools that can accommodate… Read More


NoC IP boosts SoC reliability, fault tolerance

NoC IP boosts SoC reliability, fault tolerance
by Majeed Ahmad on 12-14-2014 at 7:00 pm

System-on-chip (SoC) devices are increasingly becoming more complex in terms of adding functionality yet they need to be more reliable and fault tolerant for automotive, aerospace and industrial electronics.

Arteris Inc.—which invented the network-on-chip (NoC) interconnect technology back in 2006—is now offering FlexNoC… Read More


Filling the Gap between Design Planning & Implementation

Filling the Gap between Design Planning & Implementation
by Pawan Fangaria on 11-29-2014 at 7:00 pm

As every other person is talking about IoT today, Michael Munsey of Dassault Systemes looks at this trend in the context of critical success factors and Dassault’s strategy towards providing semiconductor solution that integrates the design chain and continues to keep the semiconductor eco-system healthy and profitable. … Read More


Xilinx Boards Make a Great Christmas Gift!

Xilinx Boards Make a Great Christmas Gift!
by Luke Miller on 11-27-2014 at 7:00 pm

Ok, first thing first, Happy Thanksgiving! For the Miller’s as I get older, it is new traditions as some old ones have passed on. Memories are great and new ones to make. So you know the great debate right?

These poor people working Thanksgiving to sell some tablet or smart phone to save a few bucks. Those that must work, my condolences… Read More


HLS Tools Coming into Limelight!

HLS Tools Coming into Limelight!
by Pawan Fangaria on 11-20-2014 at 10:00 pm

For about a decade I am looking forward to seeing more of system level design and verification including high level synthesis (HLS), virtual prototyping, and system modeling etc. to come in the main stream of SoC design. Although the progress has been slow, I see it accelerating as more and more tools address the typical pain points… Read More


Xilinx UltraFast Design Methodology Guide will save you time and money

Xilinx UltraFast Design Methodology Guide will save you time and money
by Luke Miller on 10-27-2014 at 7:00 pm

Well today, i’m easing my way back in from vacation. Took a camper, 6 kids, 1 wife with bun in the oven and saw the great USA. 17 States, roughly 5500 miles. It was great fun and tiring at the same time. The Grand Canyon was a blessing but I really enjoyed the ‘The Four Corners‘ where UT, CO, NM, AZ all meet. I had each kid… Read More


A Complete Scalable Solution for IP Signoff

A Complete Scalable Solution for IP Signoff
by Pawan Fangaria on 10-20-2014 at 7:00 am

In an SoC world driven by IP, where an SoC can have hundreds of IP (sourced not only from 3[SUP]rd[/SUP] party but also from internal business units which can have a lot of legacy) integrated together, it has become essential to have a comprehensive and standard method to verify and signoff the IP. Additionally, these checks must … Read More


StarVision to Debug and Analyze Designs at All Levels

StarVision to Debug and Analyze Designs at All Levels
by Pawan Fangaria on 10-09-2014 at 4:00 pm

In today’s SoC world where multiple analog and digital blocks along with IPs at different levels of abstractions are placed together on a single chip, debugging at all levels becomes quite difficult and clumsy. While one is working at the top level and needs to investigate a particular connection at an intermediate hierarchical… Read More


What’s Behind Carbon System Exchange – How Will it Scale?

What’s Behind Carbon System Exchange – How Will it Scale?
by Pawan Fangaria on 10-01-2014 at 4:00 pm

Earlier this year, when I was looking at Carbon’spast year performance which provided record breaking revenue with whopping jump in bookings, one thing was certain that Carbon Performance Analysis Kits (CPAKs) would drive major growth in future, not only for Carbon, but also for the semiconductor industry. It will initiate … Read More