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Hours after agreeing to build a fab in US TSMC will stop selling to Huawei- Repercussions will reverberate through all tech: Semis, semi equip, chip customers, all collateral damage.
It has been reported by Nikkei and other sources that TSMC has stopped taking orders from Huawei in order to comply with US export controls.
HUAWEI… Read More
As transistor dimensions shrink to follow Moore’s Law, the functionality of the gate used to switch on or off the current is actually being degraded by the short channel effect (SCE) [1-5]. Moreover, the simultaneous reduction of voltage aggravates the degradation, as will be discussed below.
A Practical Lower Limit of… Read More
Talking Sense With Moortec…Are You Listening?!by Tim Penhale-Jones on 05-04-2020 at 10:00 amCategories: FinFET, IP, Moortec
It almost doesn’t matter what your job may be, whether in the public sector or a private company, or how technical or how dangerous, many of life’s adages and sayings can be interpreted to have some direct meaning for all of us.
Over the years in our personal lives, we have been constantly advised that prevention is better than cure…certainly… Read More
Covid issues create “lumpy” quarters due to delays
Orders & demand remain solid and strong
2020 Year financials intact so far but ignore Qtrs
Taking prudent actions- no buybacks or guidance
As expected, Covid impacts both shipments & supply chain, ignore the near term lumpiness…
ASML reported revenues… Read More
State-of-the-art chips will always include some portions which are memory arrays, which also happen to be the densest portions of the chip. Arrayed features are the main targets for lithography evaluation, as the feature pitch is well-defined, and is directly linked to the cost scaling (more features per wafer) from generation… Read More
I had the good fortune to catch a live webinar recently that was quite compelling – Conversation with Dr. Walden Rhines: Predicting Semiconductor Business Trends After Moore’s Law! Dr. Rhines, known to most as Wally, doesn’t need much of an introduction. Any semiconductor or EDA professional knows who he is and what he’s accomplished.… Read More
I had the opportunity to preview the upcoming SemiWiki webinar titled: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs. John Park’s message, describing this powerful Cadence solution, really impressed me. That’s why I want to encourage you to register for it and join this SemiWiki … Read More
Because of significant $4 billion in equipment pull-ins in Q4 from sales in Asia, I was reducing my semiconductor wafer front-end (WFE) equipment revenue growth from an earlier +5% to 0% in 2020. Now, based on CORVID-19, I am further reducing revenue growth to -6.9%.
Chart 1 also shows the cyclical nature of semiconductors and semiconductor… Read More
Blocking chip sales to Huawei back on front burner
Covid19 & China Trade are equally bad
Long lived Uncertainty could “plague” industry sales going forward
Political Predictability worse than Disease Predictability
Reuters broke a story today that the proposed licensing of chip equipment to prevent “bad… Read More
It is a demand driven downturn – harder to predict
It may not be “business as usual” after this virus
What systemic changes could the industry face?
Trying to figure out another cycle-driven by inorganic catalyst
Investors and industry participants in the semiconductor industry who are used to normal cyclical… Read More