Due to the higher energy of EUV (13.3-13.7 nm wavelength) compared to ArF (193 nm wavelength) light, images produced by EUV are more susceptible to photon shot noise.
Figure 1. (Left) 40 nm dense (half-pitch) line image projected onto wafer at 35 mJ/cm2; (Right) 20 nm dense (half-pitch) line image projected onto wafer at 70 mJ/cm2.… Read More
Dan and Mike are joined by Graham Curren, founder and CEO of ASIC specialist Sondrel. Graham discusses the challenges of designing ASICs at the leading edge from a technology, design team and customer perspective. He explores where the real challenges are in building these types of chips and how Sondrel meets those challenges.… Read More
-Chip shortage on 60 Minutes- Average Joe now aware of chip issue
-Intel sprinkling fairy dust (money) on New Mexico & Israel
-Give up on buy backs and dividends
-Could Uncle Sam give a handout to Intel?
You normally don’t want to answer the door if 60 Minutes TV crew is outside as it likely doesn’t mean good things.… Read More
– Business is about as good as it gets- $75B WFE in 2021?
– China remains strong at 32% despite SMIC lack of license
– NAND remains 48% of revs versus 31% foundry
– DRAM steady @ 14% – Service was record $1.3B
Strong results in a strong market
Lam reported revenues of $3.85B and EPS of $7.49 for the March… Read More
Design verification (DV) is still one of the biggest challenges in the ASIC based product world. In last two decades, we have seen many changes in terms of HVLs and methodologies used for design verification. System Verilog is the most popular HVL these days and UVM is the most popular verification methodology.
Even after such an… Read More
Semiconductor startups used to rule the roost in Silicon Valley. The very name, Silicon Valley, comes from the birth of the semiconductor industry in the San Francisco bay area 60+ years ago. Large percentage of venture financing used to go to semiconductor startups, even as recently as 15 years ago. As a chip designer doing startups… Read More
In this article, we will explore the use of self-aligned litho-etch-litho-etch (SALELE) double patterning for BEOL metal layers in the 7nm node (40 nm minimum metal pitch ) with DUV, and 5nm node (28 nm minimum metal pitch ) with EUV. First, we mention the evidence that this technique is being used; Xilinx  disclosed the… Read More
Dan and Mike are joined by Terry Daly for a thoughtful and informative overview of global semiconductor supply challenges and an excellent overview of the CHIPS for America Act, an ambitious piece of US legislation aimed at establishing investments and incentives to support U.S. semiconductor manufacturing, research and development,… Read More
Semiconductor sales in 2020 were $439.0 billion, up 6.5% from $412.3 billion in 2019, according to World Semiconductor Trade Statistics (WSTS).
We at Semiconductor Intelligence have been tracking the accuracy of semiconductor market forecasts from various sources for several years. We look at publicly available projections… Read More