Consider RISC-V ISA as a new ‘unforbidden fruit’. Unlike other fruits (ISAs) that grow in proprietary orchards, RISC-V is available to all, i.e. open-source. Much like a delicious fruit can be transformed into a wide array of delectable desserts, so can RISC-V be utilized to create a plethora of effective applications across … Read More
Tag: risc-v
Podcast EP190: The Growth and Impact of RISC-V and a Peek at the Upcoming RISC-V Summit with Calista Redmond
Dan is joined by Calista Redmond, CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including vice president of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement… Read More
CEO Interview: Venkata Simhadri of MosChip
Mr. Venkata Sudhakar Simhadri is a serial entrepreneur with a proven track-record in the semiconductor industry. He was the Founder, President & CEO of Gigacom Semiconductor LLC & Founder / Director of Gigacom India (Both the Companies acquired by MosChip) and the driving force behind establishing IP licensing and … Read More
RISC-V 64 bit IP for High Performance
RISC-V as an Instruction Set Architecture (ISA) has grown quickly in commercial importance and relevance since its release to the open community in 2015, attracting many IP vendors that now provide a variety of RTL cores. Roger Espasa, CEO and Founder of Semidynamics, has presented at RISC-V events on how their IP is customized… Read More
LIVE WEBINAR: Accelerating Compute-Bound Algorithms with Andes Custom Extensions (ACE) and Flex Logix Embedded FPGA Array
RISC-V have great adoption and momentum. One of the key benefits of RISC-V is the ability for SoC designers to extend its instruction sets to accelerate specific algorithms. Andes’ ACE (Andes Custom Extensions) allow customers to quickly create, prototype, validate and ultimately implement custom memories, dedicated ports… Read More
WEBINAR: The Power of Formal Verification: From flops to billion-gate designs
Semiconductor industry is going through an unprecedented technological revolution with AI/ML, GPU, RISC-V, chiplets, automotive and 5G driving the hardware design innovation. The race to deliver high performance, optimizing power and area (PPA), while ensuring safety and security is truly on. It has never been a more exciting… Read More
A New Verification Conference Coming to Austin
Actually not so new, just new to us in the US. Verification Futures is already well established as a Tessolve event with a 10-year track record in the UK. This year they are bringing the conference to Austin on September 14th (REGISTER HERE).
While DVCon is an ever-popular event for sharing verification ideas, it isn’t always accessible… Read More
VC Formal Enabled QED Proofs on a RISC-V Core
The Synopsys VC Formal group have a real talent for finding industry speakers to talk on illuminating outside-the-box-topics in formal verification. Not too long ago I covered an Intel talk of this kind. A recent webinar highlighted use of formal methods used together with a cool technique I have covered elsewhere called Quick… Read More
Qualitative Shift in RISC-V Targets Raises Verification Bar
I had grown comfortable thinking about RISC-V as a cost-saving and more flexible alternative to Intel/AMD or Arm in embedded applications. Where clearly it is already doing very well. But following a discussion with Dave Kelf and Adnan Hamid of Breker, RISC-V goals have become much more ambitious, chasing the same big system applications… Read More
Breker’s Maheen Hamid Believes Shared Vision Unifying Factor for Business Success
Maheen Hamid, a member of the ESD Alliance (a SEMI Technology Community) Governing Council and a member of SEMI’s North America Advisory Board, is an astute business executive. Together with her husband Adnan Hamid, they founded Breker Verification Systems, a company developing test synthesis solutions. She serves today … Read More