Driven by the need to rapidly move data across a chip, the NoC IP is already a very common structure for moving data with an SoC. And various implementations of the NoC IP are available in the market depending on the end system requirements. Over the last few years, the RISC-V architecture and the TileLink interface specification … Read More
RISC-V processor IP is abundant. Open-source code for RISC-V is also widely available, but typically project-based code solves one specific problem. Using only pieces of code, it’s often up to a development team integrate a complete application-ready stack for creating an embedded device. A commercial embedded software development… Read More
Why Attend Flash Memory Summit?
FMS is the best networking opportunity in the storage industry!
The 2022 conference is expanding beyond flash memory to address all forms of high performance memory. Summit organizers welcome your submissions on a range of memory technologies including NAND Flash, DRAM, MRAM, ReRAM, and DNA storage.… Read More
RISC-V Days Tokyo 2022by Admin on 05-18-2022 at 4:37 pm
May 31, 2022 / 12:50 〜 19:00
June 1, 2022 / 10:00 〜 17:00
June 2, 2022 / 10:00 〜 16:00
Japan Standard Time (UTC+9)
RISC-V Days Tokyo is Japan’s largest online RISC-V event. Live online presentations are hosted on May 31st (Tue), June 1st (Wed) and 2nd (Thu). There will also be a virtual “RISC-V Pavilion” for the last two days.… Read More
Looking backward and forward, the white paper from Codasip “Scaling is Failing” by Roddy Urquhart provides an interesting history of processor development since the early 1970s to the present. However it doesn’t stop there and continues to extrapolate what the chip industry has in store for the rest of this decade. For the last… Read More
From a business viewpoint we often read in the technical press about the virtues of applying AI, and in the early days most of the AI model building was done in the cloud, because of the high computation requirements, yet there’s a developing trend now to use AI accelerators at the Edge. The other mega-trend in the past decade… Read More
India’s top VLSI Training Services company Maven Silicon, a RISC-V Global Training Partner, conducted an insightful discussion with the industry experts Ms. Calista Redmond, CEO, RISC-V International and Mr. Sivakumar P R, CEO, Maven Silicon, on the topic “RISC-V Open Era of Computing”.
To introduce RISC-V, it is a free and … Read More
Success with Open-Source Formal Verification
The dream of 100% confidence is compelling for silicon engineers. We all want that big red button to push that magically finds all of our bugs for us. Verification, after all, accounts for roughly two-thirds of logic design effort. Without that button, we have to create reference models,… Read More
