Score 1 for IDMs vs Fabless Intel King of the Photonics Hill in Data Centers

Score 1 for IDMs vs Fabless Intel King of the Photonics Hill in Data Centers
by Mitch Heins on 08-18-2016 at 12:00 pm

For those of you waiting with baited breath to see the Fabless community with the likes of Broadcom or Qualcomm challenge Intel in the data center space, you were just dealt a significant blow. Intel debuted their long awaited silicon photonics modules for what they called “lightning-fast” connectivity in data centers. Intel … Read More


Xilinx is Killing Altera!

Xilinx is Killing Altera!
by Daniel Nenni on 06-28-2016 at 4:00 pm

At a recent outing with FPGA friends from days gone by, the long running Xilinx vs Altera debate has come to an end. The bottom line is that Xilinx has used the FUD (fear, uncertainty, and doubt) of the Intel acquisition quite effectively against Altera and is racking up 20nm and 16nm design wins at an alarming rate. It will be a while … Read More


Fast Track to a reconfigurable ASIC design

Fast Track to a reconfigurable ASIC design
by Don Dingee on 04-25-2016 at 4:00 pm

Licensing IP can be a pain, especially when the vendor’s business model has front-loaded costs to get started. Without an easy way to evaluate IP, justifying a purchase may be tough. With more mid-volume starts coming for the IoT, wearables, automotive, and other application segments, it’s a growing concern. Flex… Read More


Mentor Extends Verification Offering!

Mentor Extends Verification Offering!
by Daniel Nenni on 03-14-2016 at 12:00 pm

With verification consuming more and more of the design cycle and the increasingly complex industry standard interfaces that are now common place, Verification IP (VIP) is again a trending topic. Back in my IP days the age old question was: Is it better to use VIP from the IP vendor? Because you know it will work, right? Or is it better… Read More


FPGA tools for more predictive needs in critical

FPGA tools for more predictive needs in critical
by Don Dingee on 02-29-2016 at 4:00 pm

“Find bugs earlier.” Every software developer has heard that mantra. In many ways, SoC and FPGA design has become very similar to software development – but in a few crucial ways, it is very different. Those differences raise a new question we should be asking about uncovering defects: earlier than when?… Read More


5nm Chips? Yes, but When?

5nm Chips? Yes, but When?
by Pawan Fangaria on 01-31-2016 at 7:00 am

For any invention, technical proof of concept or prototyping happens years ahead of the invention being infused into actual products. When we talk about 5nm chip manufacturing, a test chip was already prototyped in last October, thanks to Cadence and Imec. Details about this chip can be found in a blog at Semiwiki (link is given … Read More


The Twists and Turns of Xilinx vs Altera!

The Twists and Turns of Xilinx vs Altera!
by Daniel Nenni on 12-08-2015 at 12:00 pm

The battle between Xilinx and Altera continues to be one of the more interesting stories to cover. It really is the semiconductor version of a reality TV show. In the beginning it was two fabless companies partnered with rival foundries going head-to-head controlling a single market that touches a variety of industries.

Then things… Read More


HLS with ARM and FPGA Technologies Boosts SoC Performance

HLS with ARM and FPGA Technologies Boosts SoC Performance
by Pawan Fangaria on 11-23-2015 at 7:00 am

The way SoC size and complexity are increasing; new ways of development and verification are also evolving with innovative automated tools and environment for SoC development and optimization. IP based SoC development methodology has proved to be the most efficient for large SoCs. This needs collaboration among multiple players… Read More


Breaking the Limits of SoC Prototyping

Breaking the Limits of SoC Prototyping
by Pawan Fangaria on 11-17-2015 at 12:00 pm

Earlier this month during my conversation with Dr. Walden C. Rhines, he emphasised the need for our next generation designers to think at system level and design everything keeping the system’s view in mind. The verification will go through major transformation at the system level. I can see the FPGA prototyping systems already… Read More


Verification with Tcl for what? – part 2

Verification with Tcl for what? – part 2
by Anatoly Myshkin on 11-10-2015 at 7:00 am

In Orion Bytes we use Tcl both for the internal research, product and different verification services. We use also SystemVerilog UVM and Python based Cocotb for different approaches. I think it’s no need to deep into the SystemVerilog and UVM principles here – today’s main verification fashion is well described through… Read More