Solido Design Automation is rapidly making a name for itself in EDA. Amit Gupta is founder and CEO of Solido Design Automation, based in Saskatoon, Canada. You should also know that Solido is one of the founding members of SemiWiki.com. In the last six years we have published 44 Solido related blogs that have racked up more than 200,000… Read More
The pure-play foundry business just got stronger and so did semiconductor manufacturing in the United States. As we all know, the fabless semiconductor industry started by utilizing extra capacity from traditional semiconductor manufacturers (IDMs). However, putting your designs in the hands of a competitor is not a good … Read More
Two weeks ago the SEMI ISS Conference was held at Half Moon Bay in California. On the opening day of the conference Gary Patton CTO of GLOBALFOUNDRIES gave the keynote address and I also had the chance to sit down with Gary for an interview the next day.
If you click FinFET in the SemiWiki.com Latest News: navigation bar at the top of this page you will get a list of 86 blogs that have been viewed more than 600,000 times. If you go to the last blogs on the list, meaning the first blogs to be published, you will see a three part series, “Introduction to FinFET Technology” written by Tom Dillinger… Read More
Platform Design Automation, Inc (PDA). recently closed a US$6 million pre Series A investment round, and the company has shifted its focus from providing SPICE modeling related software and services to forming a complete AI-driven ecosystem from probing to simulation. Albert Li was the GM of Accelicon, a leading EDA tool and … Read More
Lam & Applied talked about “sustainable” growth Both expect share gains & growth in a flattish market. We examine the “new, lower, cyclicality”. Although Applied and Lam are fierce competitors , coming at things from different directions, they sounded awfully similar last week.
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Mahesh Tirupattur, EVP at low-power SERDES pioneer Analog Bits lead off the panel discussion at the recent FD-SOI Forum in Shanghai with the assertion that for anything “always on” in IoT, FD-SOI’s always better. They had a great experience porting their SERDES IP to 28nm FD-SOI (which they detailed last spring – see the ppt here… Read More
Standard cell and memory IP are key enablers for new process node availability. These two items must be in place early and be completely ready for a process node to scale to volume. Development of both leaves no room for error and they require the highest performance possible. Foundries are extremely focused on this and spend a lot… Read More
When Charlie Janac talks, people listen, absolutely. Charlie’s 30 year career spans EDA, IP, semiconductor equipment, nano-technology, and venture capital. For the last 11 years he has been CEO of interconnect IP provider Arteris who invented the industry’s first commercial network on chip (NoC) SoC interconnect IP… Read More
Low power is now a goal for most digital circuit designs. This is to reduce costs for packaging, cooling, and electricity; to increase battery life; and to improve performance without overheating. I talked to the experts on physical design for ultra-low power at Mentor Graphics recently about the challenges to P&R tools and… Read More
