Signoff Summit and Voltus

Signoff Summit and Voltus
by Paul McLellan on 11-22-2013 at 10:21 am

Yesterday Cadence had an all-day Signoff Summit where they talked about the tools that they have for signoff in advanced nodes. Well, of course, those tools work just fine in non-advanced nodes too, but at 20nm and 16nm there are FinFETs, double patterning, timing impacts from dummy metal fill, a gazillion corners to be analyzed… Read More


Cadence Design Systems’ Shares Are Surprisingly Cheap

Cadence Design Systems’ Shares Are Surprisingly Cheap
by Ashraf Eassa on 11-17-2013 at 10:00 pm

In the third and final (for now) part of this series on the EDA design tool vendors, I’d like to take a closer look at Cadence Design Systems. This is probably the most interesting of the three from both an industry perspective as well as an investment perspective for a variety of reasons. With that said I’d like to first provide some … Read More


A Brief History of eSilicon

A Brief History of eSilicon
by Daniel Nenni on 11-16-2013 at 10:00 pm

eSilicon Corporation was founded in 2000 with Jack Harding as the founding CEO and Seth Neiman of Crosspoint Venture Partners as the first venture investor and outside Board member. They both remain involved in the company today, with Jack continuing as CEO and Seth now serving as Chairman of the Board.

Both Harding and Neiman brought… Read More


Signoff Summit: The Fastest Path to Design Signoff

Signoff Summit: The Fastest Path to Design Signoff
by Daniel Nenni on 11-13-2013 at 8:00 pm

Cadence’s Signoff Summit will be held next week, November 21 at Cadence in San Jose.

This is the first of a series of all-day Signoff Summits from Cadence that focus on the multiple facets of design signoff. This first summit will include keynote addresses plus sessions covering the multiple solution components that comprise… Read More


A New IC Power Integrity Tool

A New IC Power Integrity Tool
by Daniel Payne on 11-12-2013 at 7:00 am

In EDA we have come to expect that only small start-up companies create new tools, however a team at Cadencehas developed a new IC power integrity tool called Voltus from scratch. To learn more I spoke last week with KT Moore, a Group Director at Cadence. I’ve known KT for over a decade, and first met him when he was at Magma marketing… Read More


Semiconductor Fabrication Module Optimization

Semiconductor Fabrication Module Optimization
by Pawan Fangaria on 11-11-2013 at 9:00 am

The growing process integration complexity at each technology node has increased development time and cost, and this trend looks to continue. There is a looming risk of delivering unrepeatable critical unit processes (or process modules) that would require revisiting development and manufacturing requalification or in … Read More


The Pelican Has Landed: Formal on an Unannounced ARM Processor

The Pelican Has Landed: Formal on an Unannounced ARM Processor
by Paul McLellan on 11-10-2013 at 3:00 pm

At the Jasper Users’ Group, Alex Netterville of ARM presented about how ARM are using formal on an unannounced processor code-named Pelican. Don’t read the presentation trying to find out information about Pelican itself, there isn’t any. That wasn’t the topic. Alex has been using formal approaches… Read More


Data Management in Russia

Data Management in Russia
by Paul McLellan on 11-07-2013 at 5:06 pm

Milandr is a company based in Moscow that makes high reliability semiconductor components for the aerospace, automotive and consumer markets, primarily in Russia. They work with multiple foundries, including X-FAB and TSMC in technologies from 1um down to 65nm. Corporate headquarter and main IC design house is located in Russian… Read More


Dassault Patent on Hierarchy Management

Dassault Patent on Hierarchy Management
by Paul McLellan on 11-05-2013 at 5:05 pm

Dassault have recently been granted a patent on their approach to managing design hierarchy. I asked them how long it took from filing the patent until it was granted and they said the whole process had taken 8 years. It is a bit of an indictment of the patent system when it takes 8 years, also known as 4 or 5 process nodes, for a patent to… Read More


nVidia: Virtual Platform/Emulation Hybrid

nVidia: Virtual Platform/Emulation Hybrid
by Paul McLellan on 11-05-2013 at 11:57 am

I was the VP marketing at VaST Systems Technology and then at Virtutech. Both companies sold virtual platform technology which consisted of two parts:

  • an extremely fast processor emulation technology that actually worked by doing a binary translation of the target binary code (e.g. an ARM) into the native instruction set of the
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