The Future of FPGA Prototyping!

The Future of FPGA Prototyping!
by Daniel Nenni on 12-06-2016 at 7:00 am

This interview originally appeared as the foreword to our book “Prototypical: The Emergence of FPGA-based Prototyping for SoC Design” but I thought it would be worth publishing for those of you who have not downloaded it yet. I also wanted to mention that our friends at S2C are currently offering a 50% discount on theRead More


Solido DA is One of Deloitte’s Fastest 50!

Solido DA is One of Deloitte’s Fastest 50!
by Daniel Nenni on 11-20-2016 at 8:00 pm

As a longtime EDA professional this really made my day. At a time where emerging EDA companies struggle for public validation, it warms my heart to see some very public recognition for an EDA job well done.

Deloitte, a leading Canadian professional financial services firm, announced the winners of their Technology Fast 50 program… Read More


CEO Interview: Simon Butler of Methodics

CEO Interview: Simon Butler of Methodics
by Daniel Nenni on 10-24-2016 at 7:00 am

It has been interesting to watch Methodics transform from an EDA company with their VersIC design management product to Life Cycle Management with ProjectIC, and now a Systems Company with WarpStor. Methodics was founded in 2006 by 2 ex-Cadence experts in the Custom IC design tools space, Simon Butler and Fergus Slorach. Today… Read More


Fabless Photonic Design Flow Takes Shape as Cadence teams up with Lumerical and PhoeniX

Fabless Photonic Design Flow Takes Shape as Cadence teams up with Lumerical and PhoeniX
by Mitch Heins on 10-21-2016 at 4:00 pm

This week Cadence Design, Lumerical Solutions and PhoeniX Software hosted a two-day photonic summit and workshop. The first day had nearly 100 registered participants and featured industry leaders from Global Foundries, UCSB, MIT, Hewlett Packard Enterprise, General Electric, Boeing, Rockley Photonics, and Juniper Networks… Read More


Rigid-Flex Cabling is Cool! (and requires unique EDA support)

Rigid-Flex Cabling is Cool! (and requires unique EDA support)
by Tom Dillinger on 08-15-2016 at 10:00 am

The three F’s of electronic product development are: form, fit, and function. Although the F/F/F assessment typically refers to the selection of the right component, it most definitely also refers to the selection of the proper cabling between assemblies. The requirements for cables are varied, and demanding: ability… Read More


Stressed out about Electrostatic Discharge (ESD) or Electrical Overstress (EOS)?

Stressed out about Electrostatic Discharge (ESD) or Electrical Overstress (EOS)?
by bkeppens on 07-28-2016 at 12:00 pm

Do not lose sleep worrying that your integrated circuits might fail during EOS/ESD events. Join us for the 38th annual EOS/ESD Symposium in Anaheim, CA in September. Experts on the field will address the latest research on EOS and ESD in the rapidly changing world of electronics.

As electronics continue to become commonplace in… Read More


Semiconductor IP QA Standards Get a Boost at #53DAC

Semiconductor IP QA Standards Get a Boost at #53DAC
by Daniel Payne on 06-22-2016 at 12:00 pm

At the #53DAC earlier this month held in Austin, Texas I met up with Renee Donkers, the founder of Fractal Technologies. His company has been focused on improving the quality of semiconductor IP cells through the use of automated checking software. The highest area of growth in EDA as measured by the ESD Alliance is in the reusable… Read More


The Young and the Restless, PDA vs EDA, Photonic Soaps continued…

The Young and the Restless, PDA vs EDA, Photonic Soaps continued…
by Mitch Heins on 06-16-2016 at 7:00 am

If you’ve followed my last article, The Guiding Light and Other Photonic Soaps, you read my comments about the use of waveguides to “guide the light” in photonic integrated circuits (PICs). This article continues the soap opera theme, this time with the Young and the Restless. My point here is that I am continually struck by the dichotomies… Read More


"Re-Inventing" Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis

"Re-Inventing" Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis
by Tom Dillinger on 05-23-2016 at 7:00 am

A common SoC design methodology in current use starts with preparation of the physical floorplan — e.g., block/pin placement, global clock domain and bus signal planning, developing the global/local power distribution (and dynamic power domain management techniques). Decoupling capacitor estimated densities and… Read More


Where are the Entrepreneurs?

Where are the Entrepreneurs?
by Randy Smith on 05-22-2016 at 10:00 am

This week I attended the UpWest Labs event in San Francisco. UpWest Labs provides seed funding and incubation for a wide range of domains including Enterprise Software, Internet of Things, Infrastructure Technologies, Artificial Intelligence, Consumer Applications, Drones, Cyber Security, Augmented Reality / Virtual … Read More