Do not lose sleep worrying that your integrated circuits might fail during EOS/ESD events. Join us for the 38th annual EOS/ESD Symposium in Anaheim, CA in September. Experts on the field will address the latest research on EOS and ESD in the rapidly changing world of electronics.
As electronics continue to become commonplace in… Read More
At the #53DAC earlier this month held in Austin, Texas I met up with Renee Donkers, the founder of Fractal Technologies. His company has been focused on improving the quality of semiconductor IP cells through the use of automated checking software. The highest area of growth in EDA as measured by the ESD Alliance is in the reusable… Read More
If you’ve followed my last article, The Guiding Light and Other Photonic Soaps, you read my comments about the use of waveguides to “guide the light” in photonic integrated circuits (PICs). This article continues the soap opera theme, this time with the Young and the Restless. My point here is that I am continually struck by the dichotomies… Read More
A common SoC design methodology in current use starts with preparation of the physical floorplan — e.g., block/pin placement, global clock domain and bus signal planning, developing the global/local power distribution (and dynamic power domain management techniques). Decoupling capacitor estimated densities and… Read More
This week I attended the UpWest Labs event in San Francisco. UpWest Labs provides seed funding and incubation for a wide range of domains including Enterprise Software, Internet of Things, Infrastructure Technologies, Artificial Intelligence, Consumer Applications, Drones, Cyber Security, Augmented Reality / Virtual … Read More
Mixed-signal design creates all sorts of interesting problems for implementation and verification flows, particularly when it comes to design for low power. We tend to think of mixed-signal as a few blocks like PLLs, ADCs and PHYs on the periphery of the design. Constrain and verify the digital power requirements up to analog … Read More
With the advent of SoCs, design abstractions and verification has moved up at the system level. It’s imperative that EDA moves up the value chain to start design automation at system level. The System Design Automation will be the new face of EDA in coming years.… Read More
I’m attending the 53rd Design Automation Conference (DAC) in Austin, Texas starting June 5th, and there are at least seven reasons that you should consider attending as well. For decades now DAC has been the premier place for all the players in our semiconductor ecosystem to get together: Academics, Commercial vendors … Read More
When I first heard about a foundry possibly licensing FD-SOI I would have bet it was SMIC in China. What better market for a low cost, low power, easy to manufacture alternative to FinFETs? The foundry of course was Samsung which also made complete sense since they have 28nm gate-first capacity that matches up nicely to 28nm FD-SOI.… Read More
In the 1999 comedy, The Spy Who Shagged Me, Dr. Evil laments about why he can’t have sharks with “laser beams” attached to their heads. I get the feeling that silicon photonic designers sometimes feel the same way about why they don’t yet have integrated on-chip laser light sources. While off-chip light… Read More
