Last year at DAC I visited this little-known physical IP company called DXCorr, so I decided to visit them again this year and get an update.… Read More
Physical IP Update at DAC
Tag: dac
Deploying 14nm FinFETs in your Next Mobile SoC
At DAC in Austin a design company, foundry and EDA vendor teamed up to present their experiences with 14nm FinFETs during a breakfast on Tuesday.
Panelists included:
- Ed Sperling, Semi Mfg and Design
- Anil Jain, Cavium
- Subramani Kengeri, GLOBALFOUNDRIES
- Kelvin Low, GLOBALFOUNDRIES
- Raymond Leung, Synopsys
- Bari Biswas, Synopsys
Eldo and Pyxis from Mentor, DAC Update
Last Monday at DAC I met with Linda Fosler, Marketing Director at Mentor Graphics to get an update on what’s new with Eldo(Circuit simulator) and Pyxis (custom IC layout and schematic).
Linda Fosler, Mentor Graphics… Read More
Calibre Update at DAC
Mentor Graphics throws a very nice dinner party at DAC each year for journalists, bloggers and top customers, so this year I spoke with Michael Buehler-Garcia about what’s new with Calibre.
Michael Buehler-Garcia, Mentor Graphics
… Read More
Tela Innovations, DAC Update
Lawsuits in EDA are common, and Tela Innovationsfiled a huge complaint back in February with the U.S. International Trade Commission (USITC) against HTC Corporation; HTC America, Inc.; LG Electronics, Inc.; LG Electronics U.S.A., Inc.; LG Electronics MobileComm U.S.A., Inc.; Motorola Mobility LLC; Nokia Corporation; Nokia,… Read More
GPU-Based SPICE Simulator for Library Characterization
Jeff Tuanis the CEO and President of an EDA startup called G-Analog, founded in May 2012. His background includes working at: Cadence, Epic, Synopsys, Nassda, Chartered Semi and GLOBALFOUNDRIES. Jason Lu is the R&D manager. We met at DAC last week to talk about his company’s new product called Gchar for IC library characterization… Read More
Hardware Assisted Verification
On the Tuesday of DAC I moderated a panel session on Hardware Assisted Verification in 10 Years: More Need, More Speed. Although this topic obviously could include FPGA-based prototyping, in fact we spent pretty much the whole time talking about emulation. Gary Smith, on Sunday night, actually set up things by pointing out that… Read More
Custom Physical IC Design update from Cadence
Custom IC design and layout is becoming more difficult at 20nm and smaller nodes, so the EDA tools have to get smarter and work harder for us in order to maintain productivity with the fewest iterations to reach our specs. Dave Stylesand John Stabenow of Cadence met with me last Monday in Austin at the DAC exhibit area.
John Stabenow… Read More
ARM Update at DAC
John Heinleinfrom ARM briefed me at DAC exactly one week ago. I love to use my mobile devices (MacBook Pro, iPad and Samsung Galaxy Note II) every day, and many mobile devices are ARM-powered because of the low power consumption, and pervasive eco-system around the architecture. Apple with the MacBook Pro is still Intel-powered,… Read More
AMS IC Simulation Update from Synopsys at DAC
Last year at DAC we didn’t really know the circuit simulation roadmap for Synopsys because of all the EDA company acquisitions, however this year it’s clear to me that:
- HSPICE continues on, although it’s a lower performance circuit simulator than FineSim
- FineSim from Magma is well-loved, and faster than HSPICE