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Custom IC design and layout is becoming more difficult at 20nm and smaller nodes, so the EDA tools have to get smarter and work harder for us in order to maintain productivity with the fewest iterations to reach our specs. Dave Stylesand John Stabenow of Cadence met with me last Monday in Austin at the DAC exhibit area.
John Stabenow… Read More
ARM Update at DACby Daniel Payne on 06-10-2013 at 7:09 pmCategories: Arm, IP
John Heinleinfrom ARM briefed me at DAC exactly one week ago. I love to use my mobile devices (MacBook Pro, iPad and Samsung Galaxy Note II) every day, and many mobile devices are ARM-powered because of the low power consumption, and pervasive eco-system around the architecture. Apple with the MacBook Pro is still Intel-powered,… Read More
Last year at DAC we didn’t really know the circuit simulation roadmap for Synopsys because of all the EDA company acquisitions, however this year it’s clear to me that:
- HSPICE continues on, although it’s a lower performance circuit simulator than FineSim
- FineSim from Magma is well-loved, and faster than HSPICE
…
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On Sunday I attended an IP workshop which was presented by TSMC, Atrenta, Sonics and IPextreme. It turns out that the leitmotiv of the afternoon was SpyGlass.
Dan Kochpatcharin of TSMC was first up and gave a little bit of history of the company. They built up their capacity over the years, as I’ve written about before, and last… Read More
ARM announced several new products at DAC in a number of different spaces. In addition I got invited to a briefing with Simon Segars, 30 days from when he takes over as CEO of ARM. I asked Simon if he expected to make any major changes and he basically said ‘no’. ARM’s basic strategy in both mobile and now enterprise… Read More
DAC: Tempus Lunchby Paul McLellan on 06-06-2013 at 4:03 pmCategories: Cadence, EDA
I had time for lunch on Monday. That is to say, there was a Cadence panel session about Has Timing Signoff Innovation has become and Oxymoron? What Happened and How Do We Fix It?
The moderator was Brian Fuller, lately of EE Times but now Editor-in-Chief at Cadence (I’m not sure quite what it means either). On the panel were Dipesh… Read More
One new feature at DAC this year is that several of the keynotes are preceded by a ten minute vision of the future from one of the EDA CEOs. Today it was Wally Rhines’s turn. Wally is CEO of Mentor Graphics. He titled his talk Changing the World Through EDA. Since EDA as we know it started in the late 1970s, the number of transistors… Read More
As is now traditional, Gary Smith kicked off DAC proper (there were workshops earlier and some co-located conferences started days before). He started by dismissing the idea that it costs $170M to do an SoC design.
In fact he looked at 3 different cases. Firstly, the completely unconstrained design. Well, no design is completely… Read More
This year’s Kaufman award winner is Chenming Hu. In contrast to previous years, this was presented on the Sunday evening of DAC instead of at a separate event in San Jose. Chenming’s career was reviewed by Klaus Schuegraf, Group Vice President of EUV Product Development at Cymer, Inc (now part of ASML) and also one of… Read More
One of the other increasingly successful channels (besides Semiwiki of course) for EDA, IP and semiconductor companies to reach potential customers is John Cooley’s DeepChip. Every year he puts a lot of effort into trying to find out who is exhibiting what at DAC and which stuff seems like it is new and maybe important, and… Read More