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DAC: Gary Smith: Don’t Give Away Your Models

DAC: Gary Smith: Don’t Give Away Your Models
by Paul McLellan on 06-06-2013 at 4:10 am

 As is now traditional, Gary Smith kicked off DAC proper (there were workshops earlier and some co-located conferences started days before). He started by dismissing the idea that it costs $170M to do an SoC design.

In fact he looked at 3 different cases. Firstly, the completely unconstrained design. Well, no design is completely unconstrained but for the main part of the market (mobile of one form or another) the power budget is 5W. EDA has actually done a good job of solving power problems and the mixture of tools and methodologies has cut power consumption dramatically. Nobody gets to have an unconstrained development schedule either, it is always 9-12 months max or you are out of business.

If you have $50M to spend, you get 5W (nobody gets more) which gives you 3M gates at 1.8GHz and the same 9-12 months to spend your $50M.

Lower still, at $25M, you still get a reasonable amount of real estate to play with. $25M is important because VC funding taps out at that point (actually I’m not sure how much VC funding is going on for fabless companies period, but for sure they are not going to fund a $100M development). But if a startup picks its design carefully then it can compete.

Gary then talked about if, how and when the EDA industry will take over the embedded software industry, which is struggling with lack of profitability due to the availability of good enough open source solutions, especially based on Linux.

Emulation boxes are the key to effective virtual prototypes. And now Mentor, Cadence and Synopsys all have one. Gary is the perfect straight man to my panel this year, which is on hardware assisted verification, of which emulation boxes are a big part.

The reality today is that silicon virtual prototypes don’t quite work as cleanly as they should. Architects don’t have accurate enough power models to do their work, and so when implementation proceeds architecture needs to be reworked, and the hardware-software partitioning redone, accelerators added and so on.

Gary reckons that EDA’s secret sauce is that we have the models. Give away the tools but not the models is his message for 2013.

Gary’s forecast for EDA (or technically Laurie Balch’s) is:
[TABLE] class=”cms_table_grid” style=”width: 200px”
|-
| class=”cms_table_grid_td” | Year
| class=”cms_table_grid_td” | Market
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 2013
| class=”cms_table_grid_td” | 6.1B
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 2014
| class=”cms_table_grid_td” | 6.4B
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 2015
| class=”cms_table_grid_td” | 6.7B
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 2016
| class=”cms_table_grid_td” | 7.5B
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 2017
| class=”cms_table_grid_td” | 8.3B
|-

In this EDA is defined as:

  • True EDA
  • No services
  • No ARM (it’s too big and not really EDA)
  • All other IP (Lip-Bu is going to buy them all anyway)
  • But not counting any non-commercial, internal IP development

The encore performance of Gary’s presentation will be at the DAC pavilion panel on the show floor at 9.15 this morning. If you can’t find the pavilion is is technically booth 509.

I am moderating a panel on hardware assisted verification at 4pm on Tuesday on the pavilion panel.

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