Tag: cadence

Podcast EP234: An Update on Chips and Science Act Progress with Mike O’Brien

Podcast EP234: An Update on Chips and Science Act Progress with Mike O’Brien
by Daniel Nenni on 07-05-2024 at 10:00 am

Dan is joined by Mike O’Brien. Mike was recently the vice president of aerospace and government at Synopsys, He has 40 years of experience in the semiconductor, software and computer industries. In his 27 years in EDA and IP at Synopsys and Cadence, Mike helped build new lines of business including outsourced design services, research… Read More

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Semi Market Decreased by 8% in 2023… When Design IP Sales Grew by 6%!

Semi Market Decreased by 8% in 2023… When Design IP Sales Grew by 6%!
by Eric Esteve on 04-19-2024 at 6:00 am
Categories: Arm, IP, IPnest, Semiconductor Services, Synopsys

Top10 Table 2023

Design IP revenues had achieved $7.04B in 2023, with disparity between license, growing by 14% and royalty decreasing by 6%, and main categories. Processor (CPU, DSP, GPU & ISP) slightly growing by 3.4% when Physical (SRAM Memory Compiler, Flash Memory Compiler, Library and I/O, AMS, Wireless Interface) slightly decreasing… Read More

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Preventing SOC Schedule Delays Using the Cloud

Preventing SOC Schedule Delays Using the Cloud
by Ronen Laviv on 12-25-2023 at 6:00 am
Categories: EDA

compute peaks 1

In my previous article, we touched on ways to pull in the schedule. This time I’d like to analyze how peak usage affects project timeline and cost. The above graph is based on real pattern taken from one development week in Annapurna Labs 5nm Graviton.

The Graph shows the number of variable servers per hour per day. There’s a baseline… Read More

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An Insider’s View of the 2023 Global Semiconductor Alliance’s (GSA) Annual Awards

An Insider’s View of the 2023 Global Semiconductor Alliance’s (GSA) Annual Awards
by Daniel Nenni on 12-14-2023 at 10:00 am
Categories: Events

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My beautiful wife and I attended the annual Global Semiconductor Alliance (GSA) Awards event last week. Usually this is a solo event but since my wife is CFO of SemiWiki I was able to get her an invite. I go every year and she wanted to see what all of the excitement was about. She also knows quite a few industry people from attending the… Read More

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New STA Features from Cadence

New STA Features from Cadence
by Daniel Payne on 11-13-2023 at 10:00 am
Categories: Cadence, EDA

Tempus DRA Suite

Static Timing Analysis (STA) has been an EDA tool category for many years now, yet with each new generation of smaller foundry process nodes come new physical effects that impact timing, requiring new analysis features to be added. For advanced process nodes, there are five different types of analysis that must be included when… Read More

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The True Power of the TSMC Ecosystem!

The True Power of the TSMC Ecosystem!
by Daniel Nenni on 10-02-2023 at 6:00 am
Categories: Chiplet, Events, Foundries, TSMC

logo chart 092623

The 15th TSMC Open Innovation Platform® (OIP) was held last week. In preparation we did a podcast with one of the original members of the TSMC OIP team Dan Kochpatcharin. Dan and I talked about the early days before OIP when we did reference flows together. Around 20 years ago I did a career pivot and focused on Strategic Foundry Relationships.… Read More

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The TSMC OIP Backstory

The TSMC OIP Backstory
by Daniel Nenni on 09-18-2023 at 6:00 am
Categories: EDA, Events, Foundries, IP, TSMC
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TSMC OIP 2023

This is the 15th anniversary of the TSMC Open Innovation Platform (OIP). The OIP Ecosystem Forum will kick off on September 27th in Santa Clara, California and continue around the world for the next two months in person and on-line in North America, Europe, China, Japan, Taiwan, and Israel. These are THE most attended semiconductor… Read More

Podcast EP178: An Overview of Advanced Power Optimization at Synopsys with William Ruby

Podcast EP178: An Overview of Advanced Power Optimization at Synopsys with William Ruby
by Daniel Nenni on 08-25-2023 at 10:00 am

Dan is joined by William Ruby, director of product management for Synopsys Power Analysis products. He has extensive experience in the area of low-power IC design and design methodology, and has held senior engineering and product marketing positions with Cadence, ANSYS, Intel, and Siemens. He also has a patent in high-speed… Read More

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Breakthrough Gains in RTL Productivity and Quality of Results with Cadence Joules RTL Design Studio

Breakthrough Gains in RTL Productivity and Quality of Results with Cadence Joules RTL Design Studio
by Kalar Rajendiran on 08-08-2023 at 10:00 am
Categories: AI, Cadence, EDA

Joules RTL Design Studio Benefits

Register Transfer Level (RTL) is a crucial and valuable concept in digital hardware design. Over the years, it has played a fundamental role in enabling design of complex digital chips. By abstracting away implementation details and providing a clear description of digital behavior, RTL has contributed significantly to the… Read More

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Tensilica Processor Cores Enable Sensor Fusion For Robust Perception

Tensilica Processor Cores Enable Sensor Fusion For Robust Perception
by Kalar Rajendiran on 06-22-2023 at 6:00 am
Categories: AI, Cadence, EDA, IP

Tensilica DSPs

While sensor-based control and activation systems have been around for several decades, the development and integration of sensors into control systems have significantly evolved over time. Early sensor-based control systems utilized basic sensing elements like switches, potentiometers and pressure sensors and were … Read More