SPIE Advanced Lithography 2018 – EUV Status

SPIE Advanced Lithography 2018 – EUV Status
by Scotten Jones on 03-05-2018 at 7:00 am

This year the Advanced Lithography Conference felt very different to me than the last couple of years. I think it was Chris Mack who proclaimed it the year of Stochastics. EUV has dominated the conference for the last several years but in the past the conversation has been mostly centered on the systems, system power and uptime.

I … Read More


LithoVision 2018 The Evolving Semiconductor Technology Landscape and What it Means for Lithography

LithoVision 2018 The Evolving Semiconductor Technology Landscape and What it Means for Lithography
by Scotten Jones on 02-25-2018 at 5:00 pm

I was invited to present at Nikon’s LithoVision event held the day before the SPIE Advanced Lithography Conference in San Jose. The following is a write up of the talk I gave. In this talk I discuss the three main segments in the semiconductor industry, NAND, DRAM and Logic and how technology transitions will affect lithography.… Read More


IEDM 2017 – Leti Gate-All-Around Stacked-Nanowires

IEDM 2017 – Leti Gate-All-Around Stacked-Nanowires
by Scotten Jones on 02-12-2018 at 12:00 pm

At IEDM in December I had a chance to interview Thomas Ernst about the paper “Performance and Design Considerations for Gate-All-around Stacked-NanoWires FETs” by Leti and STMicroelectonics.

Leti published the first stacked nanowire in 2006, it was very new then, now stacked nanowire/nanosheets are starting… Read More


ISS 2018 – The Impact of EUV on the Semiconductor Supply Chain

ISS 2018 – The Impact of EUV on the Semiconductor Supply Chain
by Scotten Jones on 01-18-2018 at 8:00 am

I was invited to give a talk at the ISS conference on the Impact of EUV on the Semiconductor Supply Chain. The ISS conference is an annual gathering of semiconductor executives to review technology and global trends. In this article I will walk through my presentation and conclusions.… Read More


IEDM 2017 – imec Charting the Future of Logic

IEDM 2017 – imec Charting the Future of Logic
by Scotten Jones on 01-04-2018 at 12:00 pm

At the IEDM 2017, imec held an imec technology forum and presented several papers, I also had the opportunity to interview Anda Mocuta director of technology solutions and enablement. In this article I will summarize the keys points of what I learned about the future of logic. I will follow this up with a later article covering memory.… Read More


Choosing the lesser of 2 evils EUV vs Multi Patterning!

Choosing the lesser of 2 evils EUV vs Multi Patterning!
by Robert Maire on 11-03-2017 at 12:00 pm

For Halloween this week we thought it would be appropriate to talk about things that strike fear into the hearts of semiconductor makers and process engineers toiling away in fabs. Do I want to do multi-patterning with the huge increase in complexity, number of steps, masks and tools or do I want to do EUV with unproven tools, unproven… Read More


SEMICON West – EUV Readiness Update

SEMICON West – EUV Readiness Update
by Scotten Jones on 08-11-2017 at 12:00 pm

At the imec technology forum held at SEMICON West, Martin Van Den Brink, President and CTO of ASML presented on the latest developments on EUV. I also had an opportunity to sit down with Mike Lercel, ASML Director of Strategic Marketing for an interview.… Read More


SEMICON West – Advanced Interconnect Challenges

SEMICON West – Advanced Interconnect Challenges
by Scotten Jones on 07-28-2017 at 12:00 pm

At SEMICON West I attended the imec technology forum where Zsolt Tokei presented “How to Solve the BEOL RC Dilemma” and the SEMICON Economics of Density Scaling session where Larry Clevenger of IBM presented “Interconnect Scaling Strategic for Advanced Semiconductor Nodes”. I also had the opportunity… Read More


Samsung Details Foundry Roadmap

Samsung Details Foundry Roadmap
by Scotten Jones on 06-09-2017 at 10:00 am

Samsung recently held a meeting where they laid out a detailed roadmap for their foundry business. On Tuesday June 1st, Daniel Nenni and myself had an interview with Kelvin Low, senior director of foundry marketing and business development to discuss the details of Samsung’s plans.… Read More


SPIE 2017 – ASML Interview and Presentations

SPIE 2017 – ASML Interview and Presentations
by Scotten Jones on 04-19-2017 at 7:00 am

At the SPIE Advanced Lithography conference I sat down with Mike Lercel, Director of Strategic Marketing for ASML for an update. ASML also presented several papers at the conference and I attended many of these. In this article, I will discuss my interview with Mike and summarize the ASML presentations.… Read More