I was invited to give a talk at this year’s ISS conference, the talk seemed to be very well received and I was asked to blog about it for SemiWiki. Parts of the talk will be familiar to SemiWiki readers from some of my previous blogs but I also went into more detail around some scaling challenges. The following is a summary of what… Read More
Tag: 5nm
The 2017 Leading Edge Semiconductor Landscape
In early September of 2016 I published an article “The 2016 Leading Edge Semiconductor Landscape” that proved to be very popular with many views, comments and reposting’s. Since I wrote that article a lot of new data has become available enabling some projections to be replaced by actual values and new analysis… Read More
Advanced Semiconductor Process Cost Trends
The cost trend for leading edge semiconductor technologies is a subject of some controversy in the industry. Cost is a complex issue with many interacting factors and much of the information out in the industry is in my opinion misleading or incorrect. In this article, I will discuss each of the factors as well as present a view of … Read More
The 2016 Leading Edge Semiconductor Landscape
The leading edge semiconductor logic landscape has in recent years collapsed to just four companies. The following is a summary of what is currently known about each company’s plans and how they compare. ASML has analyzed many logic nodes and developed a formula that normalizes processes to a “standard node”.… Read More
SEMICON West – Harry Levinson and Mike Lercel Interview
On Tuesday morning at SEMICON I had the opportunity to sit down with Harry Levinson, Sr. Director of Technology Research and Sr. Fellow at Global Foundries and Michael Lercel, Director of Strategic Marketing at ASML to discuss the state of lithography.
I opened the discussion with a question about how we are going to address lithography… Read More
IMEC-Horizontal Nanowires for 5nm at the VLSI Technology Symposium
At the VLSI Technology Symposium, IMEC presented a paper entitled “Gate-All-Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Silicon Wafers”. I have wanted to blog about this paper since the symposium was held but also wanted to tie it in with an interview… Read More
SEMICON West 2016 Preview
Next week is SEMICON West and I plan to be there all week. SEMICON West is a great opportunity to see the latest in equipment and materials on the show floor, to attend all the talks and receptions and to meet with various industry experts.… Read More
IMEC Technology Forum (ITF) – EUV When, Not If
For me personally EUV has been something of a roller coaster ride over the last several years. I started out a strong believer in EUV but then at the SPIE Advanced Lithography Conference in 2014 TSMC gave a very negative assessment of EUV, and there was a SEMATECH paper on high NA EUV that struck me as extremely unlikely to succeed. I … Read More
EUV is coming but will we need it?
I have written multiple articles about this year’s SPIE Advanced Lithography Conference describing all of the progress EUV has made in the last year. Source power is improving, photoresists are getting faster, prototype pellicles are in testing, multiple sites around the world are exposing wafers by the thousands and more. … Read More
SPIE – Interview with Greg Mcintyre of IMEC
One of the things I really like about major technical conferences is the opportunity to meet with people for networking and interviews. On Wednesday at the Advanced Lithography Conference I had the opportunity to interview Greg Mcinttyre, the director of advanced patterning at IMEC.
IMEC researchers are the first author on 32… Read More