The way we are seeing technology progression these days is unprecedented. It’s just about six months ago, I had written about the intense collaboration between ANSYSand TSMCon the 16nm FinFET based design flow and TSMC certifying ANSYS tools for TSMC 16nm FF+ technology and also conferring ANSYS with “Partner of the Year” award.… Read More
On March 12 SEMI held a New England Forum breakfast event entitled “Wafers to Wallstreet” with four speakers. The main focus of the discussion was on the “Internet of Things” and the following are my impression from the talks in a bullet point format.
Device Scaling and Performance in the Era of IoT – Gary Rosen, Applied Materials… Read More
The relationship between TSMC and UMC is one of the more interesting ones in the fabless semiconductor ecosystem in my opinion. Both are headquartered in Hsinchu Taiwan and it is very hard to visit one company without seeing the other as they have facilities right across the street from each other. They also share humble beginnings… Read More
Apparently that is the case. Honestly my choice would have been Mentor but I can easily make an argument for Cadence based on my discussions with the foundries and their top customers but more on that later.
Fortune Magazine last week added Cadence to the 2015 list of “100 Best Companies to Work For” citing a cultural transformation… Read More
The SPIE Advanced Lithography Conference is the world’s premier conference for patterning techniques utilized to manufacture semiconductors. At any given time during the conference there are multiple parallel sessions so it is impossible to see all of the papers presented. Prior to the conference I reviewed and blogged on … Read More
Next week is the SPIE Advanced Lithography Conference in San Jose, the premier conference for advanced lithography used to produce state-of-the-art semiconductors. Last year I blogged after the conference about some of the key points I heard at the conference and this year I plan to do the same.
Doing a modern SoC design is all about assembling IP and adding a small amount of unique IC design for differentiation (plus, usually, lots of software). If you re designing in a mature process then there is not a lot of difficulty finding IP for almost anything. But if you are designing in a process that has not yet reached high-volume… Read More
Xilinx announced their quarterly results last week. They slightly missed their number due mainly to a decline in wireless sales. Of course Xilinx parts don’t go in the smartphones since the cost and power are too high, but they are very heavily used in basestation, backhaul etc especially in China. Xilinx’s business… Read More
The big picture is that planar semiconductor transistors don’t really work below 20nm. The reason is that the gate does a poor job of controlling the channel since too much channel is too far from the gate and so there is a lot of leakage even when the transistor is nominally off. So the channel needs to be made thinner. One way … Read More
Last week was ASML’s investor day. I wasn’t there and they haven’t yet got the material posted on their website, so this is all second hand information. As you know, if you have read any of my comments on EUV, I have been dubious about whether EUV would ever work for production.
The three big problems seem to be:
