An earlier article described some of the technical and business highlights from the recent TSMC Symposium in Santa Clara (link). This article continues that discussion, with the top five updates.
(#5) Moore’s Law continues to N5.
TSMC provided an upbeat status on N5 development.
The typical process bring-up vehicle is a 256Mb SRAM array. TSMC reported fully functional N5 SRAM yield — “natural” yield, not requiring any fusible array location replacement.
N5 is targeted for risk production in 2019.
(#4) N7, and EUV introduction for N7+
N7 will enter risk production status in 2Q’17, specifically for the v1.0 PDK next month, and the mobile platform Foundation IP v1.0 release in May. The natural yields on the N7 SRAM bring-up vehicle exceed 70%.
The N7 mobile platform PDK will be used for more than 12 new tapeouts yet in 2017, according to TSMC.
The I_on versus I_off graph shown by TSMC indicated that N7 will provide a +33% performance boost at the same I_off compared to N16FFC, or a -58% I_off leakage reduction at the same I_on.
There will be an HPC platform-based offering for N7, with design rules focused on performance, rather than circuit density — i.e., larger contacted poly pitch (CPP), wider metals, larger vias, and via pillars for low-resistance metal layer route transitions. Compared to the 240nm standard cell height for the N7 mobile Foundation IP, the N7 HPC platform will offer both H300 and H360 library images.
The table below briefly compares the N7 “premium” mobile and HPC offerings.
TSMC will be introducing N7+ in 2Q’2018 (risk production, HVM in 2019), with the introduction of EUV lithography on select layers. TSMC showed an example of an array of vias that would require four litho/etch steps in N7 (4P4E), which will be patterned in a single EUV layer (1P1E).
N7+ will offer more aggressive design rules than N7, providing ~15-20% area reduction, especially from improved routing density. The design rules for the EUV layers are new, other DRC’s remain the same.
TSMC’s expectation would be that N7 designs could quickly migrate to N7+ for a performance/power optimization boost. Logic networks would require re-implementation using the new design rules; existing N7 SRAM and mixed-signal IP layouts would remain, and only be re-characterized to N7+ PDK models.
There certainly has been considerable speculation on the readiness of EUV lithography for HVM in 2019 (on select layers) — TSMC appeared very confident in the N7+ roadmap offering. They highlighted significant recent progress on EUV photoresist development.
(#3) “High-end” ULP technology — an oxymoron? Perhaps not.
The traditional thinking about IoT devices is that they will be relegated to very low-performance (and low-cost) application markets. TSMC is certainly supporting that focus with their 55ULP, 40ULP, and 28ULP technology offerings. Indeed, they are forecasting >70 new tapeouts (NTO’s) in these processes in 2017.
Yet, TSMC is also investing in high-end ULP process development. Working from the 16FFC technology base, TSMC will be offering a 12FFC ULP variant, with a nominal supply voltage down to 0.5V. (Simultaneously, TSMC is also dropping the VDD_min on their flagship 16FFC node to 0.55V, with data demonstrating significantly improved statistical process control.) TSMC showed data in support of tighter margins on SRAM VCC_min, with the drop in supply voltage. Also, the N12 node will offer tighter M1 and M2 pitch dimensions than N16.
From an implementation perspective, the 12FFC-ULP offering is focused on using a small track height standard cell IP library (6T), as opposed to the 7.5T and 9T track heights available for mobile and high-performance customers in 16nm. (A subsequent article will discuss the reference flow development with EDA partners to support mixing new 12FFC logic implementations with existing 16FFC IP.)
As with the N7 to N7+ migration strategy, the transition from N16 to N12 will involve re-implementation of logic blocks to the new library (and tighter metal rules), and re-characterization of SRAM and mixed-signal IP.
The N12 offering is currently in the final qualification phase.
55/40/28ULP, near_Vt operation, and “high-end” 12ULP — it would appear that whatever direction the IoT market takes, TSMC will have it covered.
(#2) On-chip voltage regulation — wave of the future?
Much like the Duke University basketball team was ranked too highly in the recent men’s NCAA tournament, perhaps this highlight is also ranked above its importance. After all, at the symposium, TSMC only made a passing reference to “adding an on-chip magnetic inductor process option, for integrated voltage regulation”.
TSMC has been working on this technology for some time, having published preliminary results (link here, also the source of the figure below).
The addition of an area-efficient inductor (using high-permeability materials) with low loss (high Q-factor) opens up a new chapter in on-chip power management, IMHO. The addition of on-chip switching voltage regulation IP introduces a myriad of potential power (and cost) optimizations.
Personally, I am looking forward to what will likely be a new and innovative set of IP offerings in this field.
(1) A half-node “technology kicker” offering returns.
In the 1990’s, when Moore’s Law and technology scaling were in full force, ASIC-based product offerings enjoyed a relatively straightforward migration path to realize a mid-life, performance boost, cost-reduced product release. Fabs would prepare design rules with the expectation that a 0.9X direct lithography shrink would be supported sometime after initial process qualification.
Existing ASIC designs did not require additional physical design updates (except around the I/O pad-to-die attach rules, perhaps, which didn’t necessarily scale) — only electrical analysis was required to confirm the updated performance.
Whereas a full-node scaling targeted new process design rules averaging a 0.7X reduction (2X area improvement), the 0.9X direct lithography shrink was denoted as a “half-node” — e.g., 250nm, 180nm, 130nm, 90nm “full” 0.7X scaling, with corresponding 0.9X half-nodes.
Over time, the ability to offer a half-node litho shrink became much more difficult. Complex design rules, and the corresponding optical corrections needed with 193nm exposure, could not directly scale — e.g., parallel run-length spacing rules, line end extensions, various contact/via enclosure rules.
Foundries chose to focus on a specific process technology target — in some cases, the natural 0.7X scale, in other, directly on the half-node goal. As a result, there were specific splits between 45/40nm and 32/28nm offerings. In short, half-node scaling was over… until now.
At the symposium, TSMC described a new 22ULP technology offering, which is a 0.9X litho shrink from their 28HPC+ design rules. (This is a planar device technology.)
From the I_on versus I_on graph, compared to 28HPC+, the 22ULP node offers +15% performance at the same device I_off, or -35% leakage power at the same performance. The minimum VDD for 22ULP drops to 0.6V.
A table comparing the 28nm offerings with 22ULP is shown below.
28ULP will be available for production ramp in 2017, with ReRAM and MRAM array IP offerings introduced later.
Yes, the nomenclature for 22ULP is pure marketing, as the name is unrelated to a 0.9X shrink from 28nm. In somewhat of a departure from TSMC’s normal style of not explicitly providing comparisons to competitive offerings, TSMC did show an I_on versus I_off graph for 22ULP and a “22FD-SOI” technology, which were nearly coincident lines. In an even further departure, TSMC commented, “Compared to this other technology, we will have a migration path for the 800 28nm tapeouts we are shipping, with an extremely broad IP portfolio.”
Nevertheless, the ability to develop the process controls to enable a half-node shrink for the 28nm deep submicron design rules is impressive. Existing 28nm customers looking for a process kicker, without the transition to complex multi-patterning lithography, will be enthusiastic about the offering, no doubt.
Lastly, a bonus highlight… actually, more of a business strategy than a specific technical development of note.
When TSMC was presenting their advanced packaging update, they said,“We are evolving from a pure IC foundry to a System Integration Foundry.”
That has some profound implications on our industry, IMHO. For customers, this offers the benefit of a single supplier contact for product development, qualification, and HVM ramp. For the traditional OSAT’s, this suggests that TSMC will be a direct competitor, for advanced packaging. For TSMC, it offers a significant path for financial growth, albeit in an area where margins are traditionally much thinner than wafer sourcing. It will be fascinating to see how this business and technical strategy evolves.
Look for another article shortly, on specific design enablement features that TSMC and EDA vendors have added, in support of advanced process nodes.
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