Evolving opportunities call for new and improved solutions to handle data, bandwidth and power. Moving forward, what will be the high-growth applications that drive product and technology innovation? The CAGRs for smartphone and data center continue to be very strong and healthy.
Demanding users in the high-end smartphone market have stringent requirements. Consumers want smartphones with faster transmission speeds and higher computing performance. Also, greater visual experiences have become a focus. Sharper video and camera enhancement with high resolution display will require 1.5-2X GPU performance improvement every year.
In recent years more and more devices are online, creating much heavier data traffic. To support this trend, cloud server CPUs will continue to increase their number of CPU cores for higher computing power. Internet speed and bandwidth will need to improve about 2X every year for higher data transfer rates. In addition, storage needs to increase significantly in order to support big data applications.
To address these advanced technology markets, TSMC is producing 16nm FinFET devices in volume and quickly ramping to meet 2016 demand. The company began its planned high-volume 16nm production in Q315 and achieved record-setting yield improvement during the ramp. As for device performance, TSMC has stated that its 16 FinFET+ has the best transistor performance among all foundries.
TSMC’s roadmap shows 10nm development is on track, featuring 2.1X logic density improvement (over 16FF+), a 20% performance increase or 40% power reduction. The Company’s next-generation 7nm technology progress is underway and fully functional SRAMs have already been demonstrated.
As foundries increase FinFET production it is important to note how process technology advancement changes the design ecosystem and how the ecosystem evolves to resolve those challenges and provide solutions to designers.
When a new process technology node is introduced, the continuous rise of technology complexity requires more EDA tool features and greater integration.
This chart shows the increase of total design rules from 65nm to 10nm. To comply with those new requirements – even though the total types of tools used are about the same – each tool needs to add lots of new features.
With the increased complexity of design rules, run time per gate is also increased. However, through the innovation and enhancement of EDA tools, run time per rule is significantly reduced.
Thus, the overall whole chip run time increase can still be managed. To meet tape-out schedules, EDA and IP companies are pulling in their development and certification schedules.
To further reduce design power, TSMC’s 16FFC process is being readied to support ultra-low voltage design.
To enable ultra-low voltage design, solutions for the following three critical items must be supplied:
●SPICE model and EDA tool accuracy at very low voltage
●Ensure circuit design robustness at ultra low voltage conditions
●Need to mitigate ultra low voltage design induced larger variation.
Currently TSMC enjoys good SPICE-to-silicon correlation down to 0.4V and has worked with its EDA partners to enhance signoff and characterization methods, and using new AOCV signoff methodology designers can obtain good correlation compared to Monte Carlo simulation. With new SPICE model and EDA tools support, The Company has re-optimized its standard-cell library to improve design robustness and reduce design variation.
Successful, early collaboration between foundries and their design ecosystem partners has enabled designers to have the tools and IP necessary to complete their projects in time to meet critical advanced technology time-to-market windows.
For more information join the 22nd annual TSMC Technology Symposium March 15th, 2016 and get first-hand updates on TSMC’s advanced and specialty technologies, advanced backend capabilities and future development plans! I hope to see you there!Share this post via: