TSMC Bringing EUV Into Production

Last week was ASML’s investor day. I wasn’t there and they haven’t yet got the material posted on their website, so this is all second hand information. As you know, if you have read any of my comments on EUV, I have been dubious about whether EUV would ever work for production.

The three big problems seem to be:

• source power and photoresist sensitivity
• cleaning masks and/or pellicles
• lack of defect free masks

I have heard other issues too, such as line-edge-roughness, but these seem more like the regular HVM ramp issues that greadually get fixed just by running a lot of wafers.

ASML announced that TSMC has ordered two more EUV scanners. They already have two and they will be upgraded with the new light sources. These are apparently on course to achieving 120W of output early next year and so can support 1000 wafers per day throughput (currently it is 80W and around 500 wafers per day). They claim 1500 in 2016 but schedules for anything to do with EUV have been notoriously unreliable.

They said that TSMC will be using these for 10nm production. I don’t think TSMC is going to try and introduce EUV at the same time as a new process node (nor 450mm if that ever happens). The initial PDKs for 10nm are already out and they involve multiple patterning. So I presume TSMC will actually introduce EUV for 16nm (probably not for production), do the HVM ramp for 10nm and then brings EUV in as an option there. Intel, by the way, have said they will not use EUV at 10nm.

In fact ASML’s CEO Peter Wennink conirmed this:We are working with a customer[presumably TSMC] towards a mid-node insertion of EUV at the 10nm logic node expected in late 2016. Other customers are preparing for initial learning in a manufacturing environment.

The next big problem has been mask contamination. The masks for EUV are reflective mirrors (actually not even all that reflective, ordinary mirrors absorb EUV just like almost anything). Without a pellicle, a thin covering for the mask, any contamination on the mask is in the focal plane and will print (see the above diagram). So masks need to be cleaned but there are a limited number of times a mask can be cleaned before the pattern starts to degrade. Intel has already said that they don’t see how to use EUV for volume manufacturing without a pellicle.

The challenge with a pellicle is that any material absorbs EUV with pSi being the best material by far. ASML said that they will manufacture pellicles too, so presumably striking that problem off the list.

I don’t know if progress has been made on the mask defect issue. The masks (and the mirrors in the optical path) are actually built up with multiple layers of Mo/Si. One of the challenges is that defects on the base layer can be too small to see with optical inspection (plus the size makes it equivalent to searching for a golfball in the whole of California). However, when the multi-layer mirror is build up the defect gets magnified to the point that it will print. There has been some work done on aligning the pattern on the mask so the defects are under the pattern, so irrelevant, but I’ve not seen anything about it recently. Anyway, I think mask inspection and mitigation are still an open issue.

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