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TSMC OIP – Analog Cell Migration

TSMC OIP – Analog Cell Migration
by Daniel Payne on 12-12-2022 at 10:00 am
Categories: Foundries, TSMC
2 Comments

Analog Cell min

The world of analog cell design and migration is quite different from digital, because the inputs and outputs to an analog cell often have a continuously variable voltage level over time, instead of just switching between 1 and 0. Kenny Hsieh of TSMC presented on the topic of analog cell migration at the recent North American OIP event, and I watched his presentation to learn more about their approach to these challenges.

Analog Cell Challenges

Moving from N7 to N5 to N3 the number of analog design rules have dramatically increased, along with more layout effects to take into account. Analog cell heights tend to be irregular, so there’s no abutment like with standard cells. Nearby transistor layout impacts adjacent transistor performance, requiring more time spent in validation.

The TSMC approach for analog cells starting at the N5 node is to use layout with fixed cell heights, support abutment of cells to form arrays, re-use pre-drawn layouts of Metal 0 and below, and that are silicon validated. Inside the PDK for analog cells are active cells, plus all the other parameters for: CMOS, guard ring, CMOS tap, decap and varactor.

Analog cells now use fixed heights, placed in tracks, where you can use abutment, and even customize the transition, tap and guardring areas. All possible combinations of analog cells are exhaustively pre-verified.

Analog Cell

With this analog cell approach there is a uniform Oxide Diffusion (OD) and POlysilicon (PO), which improve silicon yields.

Analog Cell Layout

Automating Analog Cell Layout

By restricting the analog transistors inside of analog cells to use more regular patterns, then layout automation can be more readily used, like: automatic placement using templates, automatic routing with electrically-aware widths and spaces, and adding spare transistors to support any ECOs that arrive later in the design process.

Regular layout for Analog Cells

Migrating between nodes the schematic topology is re-used, while the width and lengths per device do change. The APR settings are tuned for each analog component of a cell. APR constraints for analog metrics like currents and parasitic matching make this process smarter. To support an ECO flow, there’s an automatic spare transistor insertion feature. Both Cadence and Synopsys have worked with TSMC since 2021 to enable this improved analog automation methodology.

Migrating analog circuits to new process nodes requires a flow of device mapping, circuit optimization, layout re-use, analog APR, EM and IR fixes and post-layout simulations. During mapping an Id saturation method is used, where devices are automatically identified by their context.

Pseudo post-layout simulation can use estimates and some fully extracted values to shorten the analysis loop. Enhancements to IC layout tools from both Cadence and Synopsys now support schematic migration, circuit optimization and layout migration steps.

A VCO layout from N4 was migrated to the N3E node using automation steps and a template approach, reusing the placement and orientation of differential pair and current mirror devices. The new automated approach for migration was compared to a manual approach, where the time required for manual migration was 50 days and with automation only 20 days, so a 2.5X productivity improvement. Early EM, IR and parasitic RC checks was fundamental to reaching the productivity gains.

N4 to N3E VCO layout migration

A ring-based VCO was also migrated both manually and automatically from the N40 to N22 node, using Pcells. The productivity gain was 2X by using the automated flow. Pcells had more limitations, so the productivity gain was a bit less.

Summary

TSMC has faced the challenges of analog cell migration by: collaborating with EDA vendors like Cadence and Synopsys to modify their tools, using analog cells with fixed heights to allow more layout automation, and adopting similar strategies to digital flows. Two migration examples show that the productivity improvements can reach 2.5X when using smaller nodes, like N5 to N3. Even with mature nodes like N40, you can expect a 2X productivity improvement using Pcells.

If you registered for the TSMC OIP, then you can watch the full 31 minute video online.

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Achieving 400W Thermal Envelope for AI Datacenter SoCs

Achieving 400W Thermal Envelope for AI Datacenter SoCs
by Kalar Rajendiran on 12-05-2022 at 10:00 am
Categories: Alchip, Events, FinFET, Semiconductor Services, TSMC
2 Comments

Alchip BlockDiagram Oct 26 2022 tsmc na oip presentation

Successful ASIC providers offer top-notch infrastructure and methodologies that can accommodate varied demands from a multitude of customers. Such ASIC providers also need access to best-in-class IP portfolio, advanced packaging and test capabilities, and heterogeneous chiplet integration capability among other things. Of course, to deliver the above in a viable fashion, the provider needs to pick a focus in terms of what markets it serves. Alchip chose the high-performance markets for its dedicated focus many years ago and has stayed the course. As of last year, more than 80% of its $372M revenue was derived from high performance computing (HPC) related markets.

Prior posts on SemiWiki have spotlighted many of Alchip’s capabilities and accomplishments. Here is one of the latest achievements by Alchip for which it collaborated with Synopsys. Alchip delivered a TSMC 7nm process-based SoC capable of 2.5GHz performance, consuming less than 400 watts of dynamic power on a 480 sq.mm die. Such a performance, power, area (PPA) metric on an AI-enabled data center SoC is noteworthy, with particular attention to be paid to the 400 watts power number.

AI-enabled Data Center SoC

A high-level block diagram of the Alchip implemented SoC (see below) showcases the complexity and highlights the need for a collaborative, multi-company effort.

Of course, for the above SoC which is data center oriented, memory and I/O operations consume an even higher percentage of the total chip power consumption.

With HPC data centers handling increasingly large data sets, memory and other high-speed I/O operations reach extreme levels, leading to elevated thermal conditions inside the server rooms. In addition to the cooling mechanisms deployed within server rooms, lower thermal dissipation from data center chips will go a long way in keeping thermal levels under control. 400 watts of power dissipation is a pretty aggressive target for a data center chip, which in turn calls for aggressively reducing the power consumed by memory and other I/Os.

Alchip-Synopsys Collaboration

A number of members of the TSMC Open Innovation Platform (OIP) teamed up on the AI-Enabled Data Center SoC project, with Synopsys EDA tools, foundation IP and interface IP bringing a lot to bear.

Synopsys offers the broadest portfolio of IP across TSMC technology nodes ranging from 180nm to 3nm FinFET through its continuous innovation cycle for optimizing SoC PPA. Alchip leveraged Synopsys IP portfolio including its optimized cell set tailored for HPC market applications. Included with the IP set are memory design for testability (DFT) and power management support.

Standby Power

Synopsys memory compilers are optimized for power hungry applications: memory standby power is reduced by up to 50% in light sleep mode, by up to 70% in deep sleep mode and by up to 95% in shut down mode.

Switching Power

Clock power is a significant component of a chip’s total power. Through a fully automated multibit-mapping flow from the RTL stage, Synopsys was able to reduce clock power by more than 30%, resulting in more than 19% reduction of the total power. The optimization techniques involved mapping sequential multibits to combinational multibits through De-Banking and Re-Banking.

Optimized Cell Set

Low active power versions of the combinational cells helped reduce dynamic power significantly. Special wide muxes, compressors and adders helped minimize routing congestion and total power. Fast adders help ensured performance was met post route.

PPA Benefits

In addition to reducing power, multibit combinational cells also reduced area. The logic restructuring done as part of optimization techniques reduced congestion to achieve better timing. Flops optimized for Setup/Hold enabled faster timing closure.

Summary

Alchip met its cloud-infrastructure customer’s PPA challenge through its tight collaboration with Synopsys. For Alchip’s press release on this, visit here. With the TSMC N7 based SoC success under its belt, the partners are working together on TSMC N5 and TSMC N3 engagements. For more details contact Alchip.

Also Read:

Alchip Technologies Offers 3nm ASIC Design Services

The ASIC Business is Surging!

Alchip Reveals How to Extend Moore’s Law at TSMC OIP Ecosystem Forum

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Samsung Versus TSMC Update 2022

Samsung Versus TSMC Update 2022
by Daniel Nenni on 12-02-2022 at 6:00 am
Categories: Foundries, Samsung Foundry, TSMC
5 Comments

TSMC Versus Samsung

After attending the TSMC and Samsung foundry conferences I wanted to share some quick opinions about the foundry business. Nothing earth shattering but interesting just the same. Both conferences were well attended. If we are not back to the pre pandemic numbers we are very close to it.

TSMC and Samsung both acknowledged that there could be a correction in the first half of 2023 but over the next 5 years semiconductors and the foundry business will see very healthy growth rates. Very good news and I agree completely. The strength and criticality of semiconductors has never been more defined and the foundry ecosystem has never been stronger, absolutely.

At their recent Foundry Forum Samsung forecasted (citing Gartner) that by 2027 the semiconductor industry will approach $800B at a 9% Compound Annual Growth Rate and the foundry industry will experience a 12% CAGR. Samsung Foundry predicts advanced nodes (< 7nm) to outgrow the foundry industry at a 21% CAGR over the next five years and predicts its business will grow to approximately $26B by 2027 with a 20% CAGR.

It will be interesting to see what TSMC guides for 2023 during the Q4 2022 earnings call. Any guesses? Double digits (10-20%) growth is my guess. N3 will be in full production and it will be the biggest node in the history of TSMC, my opinion.

According to the World Semiconductor Trade Statistics (WSTS) the semiconductor industry is now expected to grow 4% in 2022 and drop 4% in 2023. After a 26% gain in 2021 this should not be a surprise. TSMC still expects 35% growth in 2022 and based on their monthly numbers that sounds reasonable.

For Samsung the FinFET era has come to an end with the R&D focus being on GAA. Samsung had a good run at 14nm even getting a piece of the Apple iPhone 6s business. And let’s not forget that Globalfoundries licensed Samsung 14nm so that success belongs to Samsung as well as GF.

Unfortunately, Samsung 10nm was an utter failure in both yield and PPAC (performance, power, area, cost). TSMC 10nm did not fair well either with the exception of Apple. The ROI between 14/16nm and 10nm just was not enough for most customers and the promise of 7nm was worth the wait.

7nm did much better and Samsung again came back to the competitive table. Samsung 14nm was still a stronger node but 8/7nm is doing very well. This can be seen with the current TSMC 7nm slump as Samsung is a cheaper alternative. Unfortunately, Samsung 5/4nm had serious PDK and yield problems so the lion’s share of the leading edge FinFET market went back to TSMC and will stay there, my opinion.

This leaves the door wide open for Intel Foundry Services to get back in the foundry game. IFS will be spending time with us at IEDM this coming week so we can talk more after that. If Intel executes on their process roadmap down to 18A this could get really interesting.

All three foundries are talking about GAA and Samsung is even in very limited production at 3nm GAA but personally I think the FinFET era will continue on for a few more years as we get the kinks worked out of GAA. In talking to the ecosystem at the conferences, HVM GAA is still years away and the PPAC (power/performance/area and cost) is still a big question. Based on the papers I have seen we should get a pretty good GAA update next week at IEDM. Scott Jones and I will be there amongst the media masses.

One of the more interesting battles between Samsung and TSMC became clear at the conferences and that is RF. I fully expect IFS to hit this market hard as well. Based on the talk inside the ecosystem, Samsung 8nm RF is a cheaper non EUV version of TSMC N6F and it seems to be experiencing a surge in popularity. TSMC N6F however is set to fill the N7 fabs so we should see a big push from TSMC in that direction. At the recent TSMC OIP analog automation, optimization, and migration were popular topics( TSMC OIP – Enabling System Innovation , TSMC Expands the OIP Ecosystem! ). But again, RF chips are very price sensitive so if the design specs can be met at Samsung 8RF and the ecosystem is willing then that is where the chips will go, my opinion.

Source: Samsung

Capacity plans were discussed in detail at both conferences. If you look at TSMC, Samsung, and Intel fab plans you will wonder how they will be filled. TSMC builds fabs based on customer demand which now includes pre payments so I have no worries there. Samsung and Intel however seem to be following the Field of Dreams strategy as in “build it and they will come”. I have no worries there either. If all of the fab expansion and build plans that I have seen announced do actually happen we will have oversupply in the next five years which is a good thing for the ecosystem and customers. TSMC, Samsung, and IFS can certainly weather a pricing storm but the 2nd, 3rd, and 4th tier foundries may be in for rougher times.

Just my opinion of course but since I actively work inside the semiconductor ecosystem I am more than just a pretty face.

Also Read:

TSMC OIP – Enabling System Innovation

TSMC Expands the OIP Ecosystem!

A Memorable Samsung Event

Intel Foundry Services Forms Alliance to Enable National Security, Government Applications

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TSMC OIP – Enabling System Innovation

TSMC OIP – Enabling System Innovation
by Daniel Payne on 11-25-2022 at 6:00 am
Categories: Events, Foundries, TSMC

TSMC OIP roadmap min

On November 10th I watched the presentation by L.C. Lu, TSMC Fellow & VP, as he talked about enabling system innovation with dozens of slides in just 26 minutes. TSMC is the number one semiconductor foundry in the world, and their Open Innovation Platform (OIP) events are popular and well attended as the process technology and IP offered are quite compelling to many semiconductor design segments. The TSMC technology roadmap showed a timeline of both FinFET and Nanosheet plans out through 2025.

Starting with N3 there’s something new called FinFlex that used Design Technology Co-Optimization (DTCO), promising an improved Power, Performance and Area (PPA) for segments like energy-efficient and high-performance. With the FinFlex approach a designer can choose from three transistor configurations, based on their design goals:

  • 3-2 fin blocks, for high-performance
  • 2-2 fin, for efficient performance
  • 2-1 fin, for lowest-power, best density

The history of fin block choices used in process nodes N16 to N3 are shown below:

EDA vendors Synopsys, Cadence, Siemens EDA and ANSYS have updated their tools to support FinFlex, and within a single SoC you can even mix the fin block choices. Along timing critical paths you can use high-fin cells, while non-critical path cells can be low fin. As an example of process scaling benefits, Lu showed an ARM Cortex-A72 CPU implemented in N7 with 2 fin, N5 with 2 fin, and finally N3E with 2-1 fin:

IP cells for N3E come from several vendors: TSMC, Synopsys, Silicon Creations, Analog Bits, eMemory, Cadence, Alphawave, GUC, Credo. There are three states of IP readiness: silicon report ready, pre-silicon design kit ready, and in development.

Analog IP

At TSMC their analog IP is using a more structured regular layout, which produces a higher yield and lets EDA tools automate the analog flow to improve productivity. The TSMC Analog Cell has a uniform poly and oxide density, helping with yield. Their analog migration flow, automatic transistor sizing and matching driven Place and Route enables design flow automation with Cadence and Synopsys tools.

Analog cells can be migrated through steps of: Schematic migration, circuit optimization, auto placement and auto routing. As an example, migrating a VCO cell from N4 to N3E using their analog migration flow took 20 days, versus a manual approach requiring 50 days, some 2.5X faster.

3DFabric

TSMC has three types of packaging to consider:

There are eight choices of packaging in 3DFabric:

A recent example using SoIC packaging was the AMD EPYC Processor, a data center CPU, which showed a 200X interconnect density improvement over 2D packaging,  a 15X density improvement over traditional 3D stacking, producing a 50-80% better CPU performance.

3D IC design complexity is addressed through 3Dblox, a methodology using a generic language for EDA tool interoperability, covering the physical architecture and logic connectivity. The top four EDA vendors (Synopsys, Cadence, Siemens, Ansys) have readied their tools for the 3Dblox approach by completing a series of five test cases: CoWoS-S, InFO-3D, SoIC, CoWoS-L 1, CoWoS-L 2.

TSMC has created a 3DFabric alliance by collaborating with vendors across the realms of: IP, EDA, Design Center Alliance (DCA), Cloud, Value Chain Alliance (VCA), Memory, OSAT, Substrate, Testing. For memory integration TSMC partners with Micron, Samsung Memory and SK hynix, to enable CoWoS and HBM integration. EDA test vendors include: Cadence, Siemens EDA and Synopsys. IC test vendors include: Advantest and Teradyne.

Summary

Semiconductor design companies like AMD, AWS and NVIDIA are using the 3DFabric Alliance, and that number will only increase over time as the push to use 2D, 2.5D and 3D packaging attract more product ideas. TSMC has a world-class engineering team working on DTCO, with enough international competition to keep them constantly innovating for new business. Market segments for digital, analog and automotive will benefit from the TSMC technology roadmap choices announced in FinFlex. 3D chip design is supported by the teamwork gathered in the 3DFabric Alliance.

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TSMC Expands the OIP Ecosystem!

TSMC Expands the OIP Ecosystem!
by Daniel Nenni on 10-28-2022 at 6:00 am
Categories: Chiplet, Events, Foundries, TSMC
4 Comments

TSMC OIP 2022 Roadmap

This was the 12th TSMC OIP and it did not disappoint. The attendance was back to pre pandemic levels, there was interesting news and great presentations. We will cover the presentations in more depth after the virtual event which is on November 10th. You can register HERE.

As I mentioned in my previous post, the Jim Keller Keynote would be worth the price of admission and it was. When I first talked about chiplets I sarcastically said that “chiplets are cheating”. We have spent our entire careers figuring out how to design and manufacture complex monolithic chips and now you can go to Chip Depo and get chiplets, open source software, IP, and even AI tools to more easily design complex chips.

Jim Keller is now the president and CTO of Torrent, an AI chip start up, and that is exactly what he is doing. In his keynote Jim talks about 10 problems to solve during this journey to silicon. Don’t miss it.

Here are my key takeaways from the event:

Contrary to what you may have read from the semiconductor outsider media, TSMC’s progress with advanced nodes is going as planned. N3 wafers are shipping to Apple, N3E, N4X, N3P, N3X, and N2 are on track.

Remember, N3 is Apple SoC specific. N3E is an enhanced version for the masses: Intel, AMD, NVIDIA, Qualcomm, etc… Over the next two years we will see more N3 tape-outs than any prior FinFET node, absolutely.

TSMC also expanded the OIP ecosystem to include a 3D Fabric Alliance. As I have mentioned many times semiconductors is all about the ecosystem and you will never see a more powerful ecosystem in the semiconductor industry or any other industry for that matter.

According to L.C. Lu, TSMC fellow and vice president of design and technology platform, more than 3,000 TSMC employees are part of OIP plus 10,000 people from the more than 100 OIP partners. The OIP now includes 50,000 titles, 43,000 tech files, and 2,800 PDKs.

This new alliance strengthens TSMC’s leadership in the chip packaging business. The press release provides nice detail on the new alliance but here are some clips:

The new TSMC 3DFabric™ Alliance is TSMC’s sixth OIP Alliance and the first of its kind in the semiconductor industry that joins forces with partners to accelerate 3D IC ecosystem innovation and readiness, with a full spectrum of best-in-class solutions and services for semiconductor design, memory modules, substrate technology, testing, manufacturing, and packaging. This alliance will help customers achieve speedy implementation of silicon and system-level innovations and enable next-generation HPC and mobile applications using TSMC’s 3DFabric technologies, a comprehensive family of 3D silicon stacking and advanced packaging technologies.

“3D silicon stacking and advanced packaging technologies open the door to a new era of chip-level and system-level innovation, and also require extensive ecosystem collaboration to help designers navigate the best path through the myriad options and approaches available to them,” said Dr. L.C. Lu, TSMC fellow and vice president of design and technology platform. “Through the collective leadership of TSMC and our ecosystem partners, our 3DFabric Alliance offers customers an easy and flexible way to unlocking the power of 3D IC in their designs, and we can’t wait to see the innovations they can create with our 3DFabric technologies.”

OIP 3DFabric Alliance
As the industry’s most comprehensive and vibrant ecosystem, the TSMC OIP consists of six alliances: the EDA Alliance, IP Alliance, Design Center Alliance (DCA), Value Chain Alliance (VCA), Cloud Alliance, and now, the 3DFabric Alliance. TSMC launched OIP in 2008 to help customers overcome the rising challenges of semiconductor design complexity by creating a new paradigm of collaboration, organizing development and optimization across TSMC’s technologies, electronic design automation (EDA), IP, and design methodology.

Partners of the new 3DFabric Alliance have early access to TSMC’s 3DFabric technologies, enabling them to develop and optimize their solutions in parallel with TSMC. This gives customers a head start on their product development with early availability of the highest-quality, readily-available solutions and services from EDA and IP to DCA/VCA, Memory, OSAT (Outsourced Semiconductor Assembly and Test), Substrate, and Testing.

 

The other interesting announcement was 3Dblox. Dan Kochpatcharin, the new Head of Design Infrastructure Management Division at TSMC, presented the new Open 3dBlox Standard:

TSMC 3Dblox™
To address the rising complexity of 3D IC design, TSMC introduced the TSMC 3Dblox™ standard to unify the design ecosystem with qualified EDA tools and flows for TSMC 3DFabric technology. The modularized TSMC 3Dblox standard is designed to model, in one format, the key physical stacking and the logical connectivity information in 3D IC designs. TSMC has worked with EDA partners in the 3DFabric alliance to enable 3Dblox for every aspect of 3D IC designs, including physical implementation, timing verification, physical verification, electro-migration IR drop (EMIR) analysis, thermal analysis, and more. TSMC 3Dblox is designed to maximize flexibility and ease of use, offering ultimate 3D IC design productivity.

Again, we will cover this in more detail after the virtual event so stay tuned.

Also Read:

TSMC 2022 Open Innovation Platform Ecosystem Forum Preview

Future Semiconductor Technology Innovations

TSMC 2022 Technology Symposium Review – Advanced Packaging Development

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TSMC 2022 Open Innovation Platform Ecosystem Forum Preview

TSMC 2022 Open Innovation Platform Ecosystem Forum Preview
by Daniel Nenni on 10-14-2022 at 6:00 am
Categories: Events, Foundries, TSMC
5 Comments

image002 2

One of my favorite events is just around the corner and that is the TSMC OIP Ecosystem Forum and it’s at my favorite Silicon Valley venue the Santa Clara Convention Center. Nobody knows more about the inner workings of the ecosystem than TSMC so this is the premier semiconductor collaboration event, absolutely.

In my 40 years as a semiconductor professional I cannot think of a more exciting time for our industry and TSMC is one of the reasons why. The ecosystem they have built is a force of nature that may never be replicated in the semiconductor industry or any other industry for that matter. Hundreds of thousands of people all working together for a common goal of silicon that could change the world!

The guest speaker for the Silicon Valley event will be none other than Jim Keller of Apple, AMD, Tesla, and Intel fame. Jim is an amazing speaker so you definitely do NOT want to miss this one.

REGISTER NOW

Learn About:

  • Emerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E, N4/N4P, N5/N5A, N6/N7, N12e, N22, and 28eF technologies
  • Latest 3DIC chip stacking and advanced packaging processes, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications
  • Updated design solutions for specialty technologies enabling ultra-low voltage, analog migration, mmWave RF, and automotive designs targeting automotive and IoT designs
  • Ecosystem-specific TSMC reference flow implementations, P& R optimization, machine learning to improve design quality and productivity, and cloud-based design solutions
  • Successful, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers

For more information on the TSMC OIP Ecosystem Forum, e-mail us at: tsmcevents@tsmc.com.

Here is the agenda as of today:

Time Plenary Session
08:00 – 09:00 Registration & Ecosystem Pavilion
09:00 – 09:15 Welcome Remarks
09:15 – 10:10 Enabling System Innovation & Guest Speaker
10:10 – 10:30 Coffee Break & Ecosystem Pavilion
TSMC Technical Talks
10:30 – 11:00 TSMC N3E FinFlex™ Technology: Motivation, Design Challenges, and Solutions
TSMC		 TSMC 3Dblox™: Unleashing The Ultimate 3DIC Design Productivity
TSMC		 TSMC Analog Migration Talk
TSMC
HPC & 3DIC Track Mobile & Automotive Track IoT, RF & Other Track
11:00 – 11:30 GUC’s 2.5D/3D Chiplets, Interconnect Solutions and Trends
GUC		 Analog Design Optimization by Integrating MediaTek’s ML-based Engine within the Virtuoso’s Analog Design Environment
MediaTek / Cadence		 Synopsys / Ansys / Keysight mmWave Reference Design Flow on TSMC N16FFC
Synopsys / Ansys / Keysight
11:30 – 12:00 A Unified Approach to 3DIC Power and Thermal Integrity Analysis Through TSMC 3Dblox Architecture and Ansys RedHawk-SC Platform
Ansys		 Achieving Best Performance-per-Watt at TSMC’s N2 and N3E Hybrid-Row Process Technology Nodes using Fusion Compiler and the Fusion Design Platform
Synopsys		 Breakthrough platform for AIoT markets
Dolphin Design
12:00 – 13:00 Lunch & Ecosystem Pavilion
13:00 – 13:30 SerDes clocking catered to robust noise handling in advanced process technologies for HPC, Datacenter, 5G and AI applications
eTopus Technologies / Siemens EDA		 An Accurate and Low-Cost Flow for Aging-Aware Static Timing Analysis
Synopsys / TSMC		 Cadence mmWave Solutions Support TSMC N16 Design Reference Flow
Cadence
13:30 – 14:00 Advanced Assembly Verification for TSMC 3DFabric™ Packages
Broadcom / Siemens EDA		 Analog Design Migration Flow from TSMC N5/N4 to N3E with Synopsys Case Study
Synopsys		 Analysis of Design Timing Effects of Threshold Voltage Mistracking between Cells
Synopsys
14:00 – 14:30 Simplifying Multi-chiplet design with a unified 3D-IC platform solution for 3Dblox technology
Cadence		 Low power high density design implementation for AI chip
Hailo Technologies / Siemens EDA		 RISC-V is delivering performance and power efficiency from Embedded to Automotive to HPC
SiFive
14:30 – 15:00 Advanced Auto-Routing for TSMC® InFO™ Technologies
Cadence		 Reliable compute – taming the soft errors
Arm		 TSMC, Microsoft Azure and Siemens EDA Collaboration – Enabling Your Jump to N3E using the Cloud and Calibre nmDRC
Siemens EDA / Microsoft
15:00 – 15:30 Coffee Break & Ecosystem Pavilion
15:30 – 16:00 3D System Integration and Advanced Packaging for next-generation multi-die system design using Synopsys 3DIC Compiler with TSMC 3DBlox and 3DFabric
Synopsys		 Self-testing PLLs for advanced SoCs
Silicon Creations		 HPC & Networking Trends Influencing High-Speed SerDes Requirements
Synopsys
16:00 – 16:30 TSMC 3DBlox Simplifies Calibre Verification and Analysis
Siemens EDA		 Cadence Cerebrus AI driven design optimization pushes PPA on TSMC 3nm node
Cadence		 Integration Methodology of High-End SerDes IP into FPGAs based on Early Technology Model Availability
Achronix / Alphawave IP
16:30 – 17:00 GUC’s GLink case study: Performance and reliability monitoring for heterogeneous packaging, combining deep data with machine learning algorithms
proteanTecs		 Kick-off your design success with Automated Migration of Virtuoso Schematics
Cadence		 Pinless Clocking and Sensing
Analog Bits
17:00 – 17:30 Achieve 400W Thermal Envelope for AI-Enabled Data Center SoCs – Challenge Accepted
Alchip / Synopsys		 Delivering best TSMC 3nm power and performance with Cadence digital full flow
Cadence		 Understanding UCIe for Multi-Die Systems Leveraging CoWoS and Substrate Packaging Technologies
Synopsys
17:30 – 18:30 Networking and Reception

REGISTER NOW

Abut TSMC

TSMC (TWSE: 2330, NYSE: TSM) created the semiconductor Dedicated IC Foundry business model when it was founded in 1987. TSMC served about 535 customers and manufactured more than 12,302 products for various applications covering a variety of end markets including smartphones, high performance computing, the Internet of Things (IoT), automotive, and digital consumer electronics.

Annual capacity of the manufacturing facilities managed by TSMC and its subsidiaries exceeded 13 million 12-inch equivalent wafers in 2021. These facilities include four 12-inch wafer GIGAFAB® fabs, four 8-inch wafer fabs, and one 6-inch wafer fab – all in Taiwan – as well as one 12-inch wafer fab at a wholly owned subsidiary, TSMC Nanjing Company Limited, and two 8-inch wafer fabs at wholly owned subsidiaries, WaferTech in the United States and TSMC China Company Limited.

In December 2021, TSMC established a subsidiary, Japan Advanced Semiconductor Manufacturing, Inc. (JASM), in Kumamoto, Japan. JASM will construct and operate a 12-inch wafer, with production targeted to begin by the end of 2024. Meanwhile, the Company continued to execute its plan for an advanced semiconductor fab in Arizona, the United States, with production targeted for 2024. www.tsmc.com

Also Read:

Future Semiconductor Technology Innovations

TSMC 2022 Technology Symposium Review – Advanced Packaging Development

TSMC 2022 Technology Symposium Review – Process Technology Development

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Micron and Memory – Slamming on brakes after going off the cliff without skidmarks

Micron and Memory – Slamming on brakes after going off the cliff without skidmarks
by Robert Maire on 10-03-2022 at 10:00 am
Categories: Foundries, Samsung Foundry, Semiconductor Advisors, Semiconductor Services, TSMC

Wiley Coyote Semiconductor Crash 2022 1

-Micron slams on the brakes of capacity & capex-
-But memory market is already over the cliff without skid marks
-It will likely take at least a year to sop up excess capacity
-Collateral impact on Samsung & others even more important

Micron hitting the brakes after memory market already impacts

Micron capped off an otherwise very good year with what appears to be a very bad outlook for the upcoming year. Micron reported revenues of $6.6B and EPS of $1.45 versus the street of $6.6B and $1.30.

However the outlook for the next quarter , Q1 of 2023….not so much. Guidance of $4.25B +-$250M and EPS of 4 cents plus or minus 10 cents, versus street expectations of $5.6B and EPS of $0.64….a huge miss even after numbers had been already cut.

A good old fashioned down cycle

It looks like we will be having a good old fashioned down cycle in which companies get to at or below break even numbers and cut costs quickly to try and stave off red ink.

At least this is the case in the memory business, which is usually the first to see the down cycle and tends to suffer much more as it is largely a commodity market which results in a race to the bottom between competitors trying to win a bigger piece of a reduced pie.

Will foundries and logic follow memory down the rabbit hole?

While we don’t expect as negative a reaction on the logic side of the semi industry, reduced demand will impact pricing of foundry capacity and bring down lead times. There will certainly be a lot more price pressure on CPUs as competitive pricing will heat up quite a bit. TSMC will likely drop pricing to take back overflow business it let go and we will see second tier foundry players suffer more.
The simple reality is that if manufacturers are buying less memory, they are buying less of other semiconductor types, its just that simple.

Technology versus capacity spending

For many, many years we have said that there are two types of spend in the semiconductor industry. Technology spending, in order to keep pushing down the Moore’s law curve and stay competitive. Capacity spending is usually the larger of the two, obviously mostly in an up cycle, in which the next generation of technology is put into high volume production.

Micron is obviously cutting off all capacity related spend and is just spending on keeping up its lead in technology, which they can never stop given that they are in competition with Samsung.

There is obviously some bricks and mortar spending to build the new fab in Idaho that will continue, but will only be filled with equipment and people when the down cycle in memory is over.

Micron did talk about announcing a second new fab in the US but that is likely to be very far behind the Boise fab announced and may never get built within the 5 year CHIPS for America window. The new Boise fab is 3-5 years away and will likely be on the slow side given the current down cycle.

Capex cut in half – We told you so, 3 months ago.

When you are in a hole, stop digging

We are surprised that everyone, including so called analysts, are shocked about the capex cuts. It doesn’t take Elon Musk (a rocket scientist ) to tell you to stop making more memory when there is a glut and prices have collapsed.
Maybe Micron’s comments about holding product off market last quarter should have been a clue and gotten more peoples attention as a warning sign (it got our attention).

Back when Micron reported their last quarter, 3 months ago we said ” We would not at all be surprised to see next years capex cut down to half or less of 2022’s”

Our June 30th Micron note

In case some readers didn’t get the memo we repeated our prediction of a 50% Micron capex cut a month ago “Micron will likely cut capex in half and Intel has already announced a likely slowing of Ohio and other projects”

Our August 30th note

Semi equipment companies more negatively impacted than Micron

When the semiconductor industry sneezes the equipment companies catch a cold

Obviously cutting Micron’s WFE capex in half is a big deal for the equipment companies as their revenues can drop faster than their customers.

While Micron cutting capex in half is a big deal, Samsung following suit with a capex cut would be a disaster. Its not like it hasn’t happened before ….a few years ago Samsung stopped spending for a few quarters virtually overnight.
We are certain Samsung will slow along with Micron, the only question is how much and do they also slow the foundry side of business.

Could China be the wild card in Memory?

While Micron and Samsung and other long term memory makers have behaved more rationally in recent years and moderated their spend to reduce the cyclicality we are more concerned about new entrants, such as China, that want to gain market share. Its unlikely that they will slow their feverish spending as they are not yet full fledged members of the memory cartel.
This will likely extend the down cycle because even if the established memory makers slow, China will not and will likely extend the glut and extend the down cycle.

Technology will help protect Micron in the down cycle

As long as Micron keeps up its technology spend & R&D spend to stay ahead of the pack or at least with the pack they will be fine in the longer run when we come out of the other side of the down cycle.
Micron has a very long history about being very good spenders and very good at technology and if they keep that up they will be fine. We highly doubt they will do anything stupid.

The stocks

We see no reason to buy Micron any time soon at near current levels.
As we have said recently, we would avoid value traps like the plague.
Semi equipment stocks should see a more negative reaction as they are the ones to see the negative impact of the capex cuts.

Lam , LRCX, is obviously the poster child for the memory industry equipment suppliers and is a big supplier to Micron and more importantly Samsung
We also see no reason to go near Samsung and Samsung may be a short as investors may not fully understand the linkage to the weakness in the memory industry. Semiconductors are the life blood of Samsung and memory is their wheelhouse whereas foundry is their foster child.

We warned people months ago “to buckle up, this could get ugly” and so it continues.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.
We have been covering the space longer and been involved with more transactions than any other financial professional in the space.
We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.
We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

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Application-Specific Lithography: 5nm Node Gate Patterning

Application-Specific Lithography: 5nm Node Gate Patterning
by Fred Chen on 09-08-2022 at 6:00 am
Categories: Foundries, Lithography, TSMC
4 Comments

Blur Limitations for EUV Exposure

It has recently been revealed that the N5 node from TSMC has a minimum gate pitch of 51 nm [1,2] with a channel length as small as 6 nm [2]. Such a tight channel length entails tight CD control in the patterning process, well under 0.5 nm. What are the possible lithography scenarios?

Blur Limitations for EUV Exposure

A state-of-the-art EUV system has limited options for 51 nm pitch. Assuming the use of sub-resolution assist features (SRAFs) [3], an ideal binary image is projected with good NILS (normalized image log-slope) and depth of focus; however, blur spoils this outcome (Figure 1). The intensity modulation is diminished by blur.

Figure 1. Impact of blur on 51 nm pitch image on a 0.33 NA EUV system. A Gaussian or exponential blur function is convoluted with the blur-free image. Only relative blur magnitudes are given here.

Blur itself cannot be expected to have a fixed magnitude, as secondary electron yield is itself a variable quantity [4]. This alone generates a massive range of possible CDs. Moreover, blur from electrons is more exponential in nature than Gaussian [5]. This further worsens the impact, as exponential blur accumulates more contributions from electrons further away from the point under consideration (Figure 2).

Figure 2. Exponential vs. Gaussian blur. Exponential blur decays faster at shorter distance while Gaussian blur decays faster at larger distances.

Consequently, with CD changes easily approaching or even exceeding 50%, EUV exposure is unsafe for gate patterning, which requires tolerances <10%. High-NA suffers from the same issue. Even if the NA went as high as the vacuum limit of 1.0 (Figure 3), blur, not wavelength/NA, dominates the image.

Figure 3. Blur degrades the ideal image even for the maximum EUV NA of 1.0.

Solution: SADP

The situation is changed entirely if the gate CD is not determined by lithography directly, but by a sidewall spacer width. The lithography pitch for spacer patterning is doubled to 102 nm, which is easily accommodated by ArF immersion lithography. This self-aligned double patterning (SADP) approach has been around for a long time [6,7]. Thus, this gate patterning approach will likely never go away.

References

[1] https://www.angstronomics.com/p/the-truth-of-tsmc-5nm

[2] https://www.dolphin-ic.com/products/standard-cell/tsmc_5ff_cell.html; https://www.dolphin-ic.com/products/standard-cell/tsmc_4ff_cell.html

[3] http://www.lithoguru.com/scientist/litho_tutor/TUTOR43%20(Nov%2003).pdf

[4] H. Fukuda, “Stochasticity in extreme-ultraviolet lithography predicted by principal component analysis of Monte Carlo simulated event distributions in resist films.” J. Appl. Phys. 132, 064905 (2022).

[5] M. Kotera et al., “Extreme Ultraviolet Lithography Simulation by Tracing Photoelectron Trajectories in Resist,” Jpn. J. Appl. Phys. 47, 4944 (2008).

[6] E. Jeong et al., “Double patterning in lithography for 65nm node with oxidation process,” Proc. SPIE 6924, 692424 (2008).

[7] https://seekingalpha.com/article/4513009-applied-materials-smic-move-another-headwind

This article first appeared in LinkedIn Pulse: Application-Specific Lithography: 5nm Node Gate Patterning.

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Intel and TSMC do not Slow 3nm Expansion

Intel and TSMC do not Slow 3nm Expansion
by Daniel Nenni on 08-09-2022 at 10:00 am
Categories: Foundries, Intel Foundry, TSMC
7 Comments

Pat Gelsinger and CC Wei SemiWiki

The media has gone wild over a false report that Intel and TSMC are slowing down 3nm. It is all about sensationalism and getting clicks no matter what damage is done to the hardworking semiconductor people, companies and industry as a whole. And like lemmings jumping off a cliff, other less reputable media outlets perpetuated this false report with zero regard for the truth.

By the way, lemmings only jump off cliffs when they become overpopulated and migrations end badly. So maybe that is what has happened here, media outlets have become over populated.

For the record:

-Q2 2022 Taiwan Semiconductor Manufacturing Co Ltd Earnings Call

“CC Wei: Next, let me talk about the tool delivery update. As a major player in the global semiconductor supply chain, TSMC work closely with all our tool supplier to plan our CapEx and capacity in advance. However, like many other industries, our suppliers have been facing greater challenges in their supply chains, which are extending toward delivery lead times for both advanced and mature nodes. As a result, we expect some of our CAPEX ($4B of $44B) this year to be pushed out into 2023.”

And an update on N3:

“CC Wei: Now let me talk about the N3 and N3E status. Our N3 is on track for volume production in second half of this year with good yield. We expect revenue contribution starting first half of 2023, with a smooth ramp in 2023, driven by both HPC and smartphone applications. N3E will further extend our N3 family with enhanced performance, power and yield. N3E will offer complete platform support for both smartphone and HPC applications. We observed a high level of customer engagement at N3E, and volume production is scheduled for around 1 year after N3. Our 3-nanometer technology will be the most advanced semiconductor technology in both PPA and transistor technology when it is introduced. Thus, we are confident that our N3 family will be another large and long-lasting node for TSMC.”

Yes, Intel had a challenging quarter and it will be a difficult year but my sources say that Meteor Lake, the first disaggregated chip with an Intel 4 CPU, TSMC N3 GPU, and a TSMC N5 base die and SoC is on track. Saphire Rapids I do not know. Since this involves stitching multiple Intel CPU tiles together there could be challenges but this seems to be a design/integration issue versus a process yield problem.

Pat Gelsinger has fixed the Intel process issues by changing the methodology to match what TSMC does, half nodes versus full nodes for advanced yield learning. As a result, I have complete confidence in Intel 4 and 3 moving forward as planned, absolutely.

-Q2 2022 Intel Conference Call Comments

Pat Gelsinger: For example, regaining our leadership begins with Moore’s Law and the capacity to deliver it at scale. Over the last 18 months, we’ve taken the right steps to establish a strong footing for our TD roadmap. We are well into the ramp of Intel 7, now shipping in excess of 35 million units. Intel 4 is ready for volume production in second half of this year and Intel 3, 20A and 18A are all at or ahead of schedule.

Pat also reorganized Intel design groups and decentralized them for increased autonomy. This will take time to see the results but I can assure you it was the correct thing to do.

I know having chicken little in the semiconductor hen house is fun to watch but it really is getting old. Check your sources and if they have zero semiconductor experience I would take it for what it is worth, entertainment.

And for those of you who want to know what really caused the automotive chip shortage:

“In the past two years they call me and behave like my best friend,” he told a laughing crowd of TSMC partners and customers in Silicon Valley recently. One automaker called to urgently request 25 wafers, said Wei, who is used to fielding orders for 25,000 wafers. “No wonder you cannot get the support.” CC Wei, TSMC Technical Symposium 2022.

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How TSMC Contributed to the Death of 450mm and Upset Intel in the Process

How TSMC Contributed to the Death of 450mm and Upset Intel in the Process
by Craig Addison on 08-05-2022 at 6:00 am
Categories: Foundries, Intel Foundry, TSMC
8 Comments

450mm wafer

Pinpointing exactly when 450mm died is tricky. Intel’s pullback in 2014 has been cited as a pivotal moment because it was the main backer of the proposed transition, as it had been for the shift to 150mm (6-inch) wafers in the early 1980s.

However, the participation of global foundry leader TSMC was also seen as crucial if 450mm wafers were to become reality, as was support from Samsung Electronics and the semiconductor equipment sector, the latter having shouldered the financial burden of the 300mm transition.

Two years after Intel’s pullback in 2014, TSMC quietly wound down its participation in the Global 450 Consortium, founded at SUNY Polytechnic Institute in New York in 2011.

The reported reasons for Intel’s decision were low utilization rates and an empty fab 42 shell, but why did TSMC turn cold on 450mm?

The answer to that question – or at least one interpretation of it – can be found in a newly published oral history interview with Shang-Yi Chiang, TSMC’s vice president of R&D at the time.

Earlier this year, Chiang sat for an interview as part of the Computer History Museum’s oral history program. The transcript of the interview is now available as public record.

“It seemed a foregone conclusion that [TSMC] would go along with the next size… which was aggressively being pushed by Intel,” Chiang is quoted saying in the transcript. “Intel tried very hard to get TSMC and Samsung to join forces. Intel already started spending a couple billion dollars in preparing for 450-millimeter wafers,” he said.

After TSMC’s founder and CEO Morris Chang presented a roadmap for 450mm at an investor conference, “all of a sudden… the industry became very hot for 450mm wafers,” according to Chiang.

However, that’s when the TSMC R&D chief revealed his reservations about the commitment.

“One day in 2013, I think around March… I went to Morris Chang’s office. I said, ‘I don’t think we should promote these 450mm wafers. In the past, our competitors [were] UMC, SMIC, and those guys are much smaller than we are. [If] we promote 450mm, we take advantage of them. But right now, we only have two competitors, Intel and Samsung. Both are bigger than we are.”

Chiang argued that 450mm would tie up too many of TSMC’s R&D staff, reducing its ability to pursue technology advancements in other areas. However, Intel – with a bigger R&D budget – would be less affected. Therefore, the main reason for going to larger wafers was so “a big guy can squeeze the small guy out”, Chiang said.

Subsequently, Morris Chang called more than 10 internal meetings to discuss the matter, but he also dispatched Chiang to consult with equipment vendors, including Applied Materials, Lam Research and KLA.

In the end, the TSMC founder decided not to support the transition to 450mm. However, the problem was how to communicate that decision without sounding “negative”.

“If you just say directly that TSMC will not do that, it is a negative image because you are not looking at the future,” according to Chiang’s interview transcript. Instead, it was decided that the decision would be framed as a shift in priorities. Instead of 450mm, TSMC would focus on “advanced technology”.

Chiang also recounted how he conveyed the decision to Intel’s technology and manufacturing chief Bill Holt. It was at a private meeting at SEMICON West 2013, hosted by ASML and attended by two representatives from Samsung Electronics as well as two each from Intel and TSMC.

Holt opened the meeting by saying he believed the industry should be aggressive in moving to 450mm, and that all the players should share the costs, according to Chiang’s recollection.

Samsung’s representatives did not say anything. When Chiang’s turn came, he gave Holt the bad news, but the Intel manufacturing chief did not take it well.

“He was very upset and walked away,” according to Chiang’s recollection.

Holt, who began his Intel career in DRAM development in 1974, retired from Intel in June 2016.

Chiang, a US citizen whose most recent assignment was with TSMC’s mainland Chinese rival SMIC, retired from the industry last year and now resides in Silicon Valley.

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