Posted on

Fabless Semiconductor Milestones of 2014!

Fabless Semiconductor Milestones of 2014!
by Daniel Nenni on 12-28-2014 at 9:00 am
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

After working in the semiconductor industry for the past thirty years and writing about it for the past six I would say that 2014 was one of the more interesting years of late. Vindication is the word that pops into my mind now that many “predictions” the fabless detractors have made over the last three years were proven wrong.

As a student of history I think it is important to look at the past to better prepare for the future which is one of the reasons why I blog. Blogging also enabled us to write our book on the history of the fabless semiconductor industry. To take a look back, SemiWiki members can click on the company names or industries (categories) in the header of the blog summaries to see what we have written on that company or market segment. You can also click on the author to see what each of us have written, simple as that.

In 2014 814 blogs were published on SemiWiki bringing the total to 2134 written by 42 different people. According to Google, SemiWiki has recorded 1,245,650 unique viewers since going online in 2011. The big data (analytics) behind all of this activity is truly amazing.

2014 also brought my 30th wedding anniversary which my beautiful wife and I celebrated in Hawaii. She runs the financial side of SemiWiki and edits everything I write. 30 more years is going to be no problem at all.

Some of the top viewed blogs I wrote in 2014 include:

[LIST=1]

  • GLOBALFOUNDRIES Acquires IBM Semiconductor Unit!
  • Intel Core M vs Apple A8!
  • Is Intel the Concorde of Semiconductor Companies?
  • TSMC Responds to Intel’s 14nm Density Claim!
  • TSMC vs Intel vs Samsung FinFETs
  • Who is Using Samsung 14nm?
  • More Apple A9 Ridiculousness!
  • Who will Manufacture Apple’s Next SoC?
  • TSMC Updates: 20nm, 16nm, and 10nm!
  • Samsung 14nm is the one delayed!

    I agree with this ranking 100%. The GF/IBM deal was by far the most exciting thing to happen in 2014. I have written about GF 46 times over the last 5 years and the IBM acquisition blog was viewed 5 times more than the average. It really could be a game changer for the fabless semiconductor industry. The pure-play foundry business model is what delivered supercomputing to our fingertips (literally) so that business model must continue at all costs. Seriously, IDM foundries do not have our collective best interests in mind as history has clearly shown.

    The most controversial event was the release of the TSMC 20nm A8 and A8x making Apple one of the leading fabless semiconductor companies. Not only was this Apple’s first pure-play foundry chip it was also the first time Apple designed two SoCs, one for the iPhone and a higher performance version for the iPads. Even though South Korea press said this would be a Samsung chip we all knew it would be TSMC and it would yield in time for the iPhone6 launch in Q3 2014. The other thing the A8 brought was a fresh perspective on the Intel process density superiority claims.

    The word vindication also comes to mind since so called industry experts claimed that 20nm would not be in high volume production “until 2015 but mostly 2016”. People also doubted the foundries would produce FinFETs in 2015 and one gentleman predicted that it wouldn’t happen until 2017 and 10nm would also be delayed. Clearly that is not the case so congratulations to the hard working people of the fabless semiconductor ecosystem that proved experts, competitors and the outside media wrong, absolutely.

    • Posted on

    Results of TSMC’s ECO Fill Flow

    Results of TSMC’s ECO Fill Flow
    by Beth Martin on 12-22-2014 at 7:00 am
    Categories: EDA, TSMC

    By Jeff Wilson, Mentor Graphics and Anderson Chiu, TSMC

    At this year’s TSMC Open Innovation Platform® (OIP) Ecosystem Forum, Mentor Graphics and TSMC co-presented some results of the ECO Fill flow developed for TSMC customers working at advanced nodes. Here is a summary of the presentation. (TSMC customers can access the presentation at TSMC-Online).

    Metal fill (inactive metal shapes) was originally added to open design areas in layouts because a certain metal density was required to pass the foundry’s density design rule checks (DRC). These foundry density requirements helped reduce wafer thickness variations created during chemical-mechanical polishing (CMP) processes. To avoid creating parasitic capacitance issues, the goal was to add only as much fill as needed to satisfy the minimum and maximum density requirements set by the foundry.

    At 45nm and below, metal fill affects multiple manufacturability issues such as stress, etch response, and rapid thermal annealing, and has an impact on design performance. Foundry fill targets have switched from ensuring a basic minimum density to achieving a maximum density. In addition, density checks for density gradient now require a smooth transition between fill densities in adjacent locations. At 20nm and below, fill requirements must also comply with multi-patterning (MP) restrictions to ensure mask balancing, and designers must begin adding multi-layer fill not just to back-end-of-line (BEOL) metal and via layers, but also to front-end-of-line (FEOL) layers. All of these changing manufacturing requirements impact the complexity of metal fill placement, as well as the number of fill elements in a design.

    These changes in fill require sophisticated new fill types and filling strategies. New techniques such as cell-based and multi-patterning-aware fill were integrated into fill engines to provide an automated fill process that can be called from place and route (P&R) tools to ensure an easy-to-use design flow that produces correct-by-construction results. However, the number of fill shapes in advanced node technologies can exceed a billion objects. So an engineering change order (ECO) that arrives late in the tapeout process and requires fill changes in the surrounding area can be a significant engineering challenge. The complexity of replacing fill and reconfirming timing may negatively affect runtime and timing closure, which can lead to a delayed tapeout delivery.

    To handle these last-minute design changes, TSMC developed an ECO fill reference flow designed to work in concert with their overall design ECO flow. The TSMC ECO fill flow addresses the same range of fill situations that their full fill flow encounters, but concentrates only on the portion of the design affected by the ECO. This flow can account for the timing impact of fill without slowing down the back-end flow.

    The TSMC ECO fill reference flow incorporates Calibre® YieldEnhancer’s SmartFill functionality and Calibre DESIGNrev™ to keep fill shapes in a separate file on disk, similar to the approach that the leading parasitic extraction tools use to
    minimize the size of the design database. This proven “merge when needed” approach provides the proper balance between accuracy and performance. The TSMC ECO fill reference flow (shown in the figure to the right) is currently supported for 16nm and 20nm processes. Users can download all the necessary files from TSMC.

    By removing and replacing only the fill in the surrounding area, and re-verifying timing only in the affected area, designers can reduce runtime, manage file size, and minimize timing impacts (see the following figure). By restricting the ECO fill operation to only the same locations where actual mask-making changes occur, the TSMC ECO fill reference flow limits the size of the region that must be evaluated for errors, edited, and refilled. This area reduction is accomplished by generating exclude regions, and clipping the fillable database to include only the area around the design ECO.

    To reduce the size of the fill database, TSMC uses a cell-based approach to fill the design. If the ECO fill flow does not properly handle fill cells, designers will see an explosion in the fill database. So, to minimize this, Calibre SmartFill only flattens the minimum number of cell instances required to remove existing fill that conflicts with the ECO design shapes. It also removes shapes based only on metal-stack-aware DRC spacings. It then refills only in the areas where ECO changes occurred, rather than refilling the entire chip.

    There is a breakeven point in this reference flow—if the area to be refilled is too large, then the efficiencies of scale may be lost. In general, ECO fill strategies are most efficient when the change affects less than 1% of the design area. For bigger changes, the runtime of the ECO fill flow may exceed that of a regular fill run. Generally, good candidates for ECO fill include small areas of change, such as changes in gate functionality that requires a localized rerouting in a limited area. When changes to an entire block indicate that it would be more efficient to simply refill the design from scratch, a hierarchical fill approach may be more appropriate. However, designers must always consider whether minimizing timing impacts and mask costs offset any runtime disadvantage.

    This table demonstrates a number of advantages to having a specialized ECO Fill flow that uses the exact same fill deck that was used to fill the design originally.


    The results from several real world test cases show that fill runtime was reduced by 34% to 89% by using the ECO fill flow rather than a full refill. In four of the five cases, the number of masks that required changes was reduced, and in one case the ECO fill approach resulted in six fewer masks requiring re-manufacturing. The TSMC ECO Fill reference flow implemented with the SmartFill functionality in Calibre YieldEnhancer provides a push-button solution that can handle any last minute design changes.

    Posted on

    IEDM: TSMC, Intel and IBM 14/16nm Processes

    IEDM: TSMC, Intel and IBM 14/16nm Processes
    by Paul McLellan on 12-16-2014 at 7:10 am
    Categories: Events, Foundries, GlobalFoundries, Intel Foundry, TSMC

    This week is IEDM. Three of the presentations today were by TSMC, Intel and IBM going over some of the details of their 14/16nm processes. They don’t provide the slides at IEDM, just the single page papers so this may end up being a somewhat random collection of facts.

    TSMC were up first. They talked about the improvements that they had made going from their 16FF to the second generation 16FF+ under the title An Enhanced 16nm CMOS Technology Featuring 2nd Generation FinFET Transistors and Advanced Cu/low-k Interconnect for Low Power and High Performance Applications. They already reported on the basic 16FF process last year so this is an update.

    The new process core devices are re-optimized to provide additional 15% speed boost or 30% power reduction. Device overdrive capability is also extended by 70mV through reliability enhancement. Superior 128Mb High Density (HD) SRAM Vccmin capability of 450mV is achieved with variability reduction for the first time. Metal capacitance reduction by ~9% is realized with advanced interconnect scheme to enable dynamic power saving.It seems they are using SADP when forming the fins:Fin patterning and formation on bulk silicon with a 48nm fin pitch is realized using pitch-splitting technique where the fin width is determined by the sidewall thickness of a mandrel. Fin profile and gate profile are carefully co-optimized to balanceamong the needs to maintain excellent short channel control, to enhance drive current and to reduce parasitic capacitance of the devices. Poly-silicon deposition and gate patterning with a gate pitch of 90nm on the 3-dimensional fin structure is followed by high-K metal gate (HK/MG) RPG process.

    Metal1 pitch is 64nm obtained using an “advanced” patterning scheme (I’m assuming LELE double patterning). Higher levels of metal at 80/90nm pitch are single patterned. There is a 15% speed gain or a 30% power reduction compared to 16FF.

    Intel    presented their 14nm Logic Technology Featuring 2nd-Generation FinFET 2 , Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588um[SUP]2[/SUP] SRAM cellsize. They said that their area per transistor shrink was slightly better than the normal shrink (at 49%), and the cost per transistor continues to fall exactly on Moore’s law. The minimum metal pitch is 52nm (only on metal2, metal1 pitch is 70nm and metal0 is 56nm). The fin pitch is 42nm, and the fins are also taller (42nm) and thinner and more square. The contact to gate pitch is 70nm. They have airgaps on just two metal layers, M4 and M6, which products 14-16% performance increase. SADP is used on critical patterning layers. Variation in Vt, which was getting worse with each planar node, improved and 22nm and improves again at 14nm.

    They admitted that they have had yield problems, which is public knowledge. 22nm is the highest yielding process in Intel history and 14nm is now almost at the same level. It is shipping in volume.


    Using gate pitch multiplied by metal pitch as a proxy for density, Intel have been slightly behind (since TSMC did 28nm when Intel did 32nm, then 20nm when Intel did 22nm, although the timing was such that Intel had earlier production). At 14/16nm this reverses (see diagram).


    IBMtalked about their High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization. Of course this is a process that GlobalFoundries will take over when the acquisition of IBM’s semiconductor division is complete.

    They have a 42nm fin pitch and 80nm contact/poly (so single pattern and cut mask). Metal1 is 64nm pitch. One interesting feature of the process is that they can created decoupling capacitors on-chip without any additional mask. They can make a 31.5uF decap. With the addition of two masks they can make multi work function. There is a 5X leakage reduction. The 14nm eDRAM unit cell has been scaled down to 0.0174um2, which provides a unique memory solution for cache starved processors.

    In the Q&A they were asked if they had SiGe in the fins and refused to comment, which may or may not be significant.

    Bottom line: Intel is ahead (by their own reckoning). IBM has the most perfect process for server processors. But I don’t expect to see competitive SoCs out of Intel before TSMC. Competitve microprocessors from IBM sure, although they are not in the merchant market. Competitive microprocessors ahead of TSMC obviously. But SoCs, let’s see how it pans out.

    More articles by Paul McLellan…

    Posted on

    TSMC Gets Ready for IoT

    TSMC Gets Ready for IoT
    by Paul McLellan on 12-10-2014 at 11:36 am
    Categories: Foundries, TSMC

    With all the talk about 14/16nm and 10nm it is important to realize that older processes are still important. Eventually 16nm may end up being cheaper than 28nm but for the time being 28nm seems to be a sort of sweet spot, not just cheaper than every process that came before it (which was true for every new node) but also cheaper than every process that will come after it (which is new territory for the semiconductor industry). If you are designing an application processor for a smartphone then you will move to the new nodes as fast as you can. But other markets, in particular products for the internet of things (IoT) don’t need that. They need low power, digital/analog/RF integration and so on. This creates new opportunities in the non-bleeding-edge process geometries.

    With the explosive growth phase of smartphones over, IoT is expected to provide a lot of the high growth consumption of semiconductor for the coming few years. PC is nearly flat, smartphone growth will mostly be at the low end of the market with the high end now being mostly a replacement market.


    TSMC has introduced ultra-low power versions of some of its mature processes. The current status is that ultra low power versions of 0.18um and 90nm are in production and 50nm, 45nm and 28nm ULP processes will take risk production in 2015. There is also integrated RF and flash. These are especially attractive for IoT designs that need extremely low power and connectivity. Some IoT applications (such as automotive) are not all that power sensitive since there is a large battery available, but others such as wearables require very long periods between recharges, and still others are predicted to need a battery that lasts for the life of the product or they scavenge power from their local environment.


    Some details of the process. First they operate at a lower Vdd which reduces both standby and active power (and leakage). They are optimized for the 0.5-0.7V range. The tailored eHVT device enables an over 70% reduction in standby power. However they can also work at higher voltages at 1.1V (40LP) and 1.2V (55LP).

    Most IoT designs don’t seem to need really high performance nor billions of transistors since both would consume too much power. But they need the combination of very lower power operation, especially in standby where they will spend most of their life, and RF (since they need connectivity through cellular, WiFi, Bluetooth or some other radio interface).


    So the bottom line is that the new processes are compatible with the existing eco-system at 28HPC. But the operating voltage is reduce by over 20%, active power by over 30%, standby power by over 70% and the capability to build an SoC that includes RF and embedded flash, perfect for the IoT market.

    Posted on

    TSMC Bringing EUV Into Production

    TSMC Bringing EUV Into Production
    by Paul McLellan on 12-08-2014 at 7:00 am
    Categories: Foundries, TSMC

    Last week was ASML’s investor day. I wasn’t there and they haven’t yet got the material posted on their website, so this is all second hand information. As you know, if you have read any of my comments on EUV, I have been dubious about whether EUV would ever work for production.

    The three big problems seem to be:

    • source power and photoresist sensitivity
    • cleaning masks and/or pellicles
    • lack of defect free masks

    I have heard other issues too, such as line-edge-roughness, but these seem more like the regular HVM ramp issues that greadually get fixed just by running a lot of wafers.


    ASML announced that TSMC has ordered two more EUV scanners. They already have two and they will be upgraded with the new light sources. These are apparently on course to achieving 120W of output early next year and so can support 1000 wafers per day throughput (currently it is 80W and around 500 wafers per day). They claim 1500 in 2016 but schedules for anything to do with EUV have been notoriously unreliable.

    They said that TSMC will be using these for 10nm production. I don’t think TSMC is going to try and introduce EUV at the same time as a new process node (nor 450mm if that ever happens). The initial PDKs for 10nm are already out and they involve multiple patterning. So I presume TSMC will actually introduce EUV for 16nm (probably not for production), do the HVM ramp for 10nm and then brings EUV in as an option there. Intel, by the way, have said they will not use EUV at 10nm.

    In fact ASML’s CEO Peter Wennink conirmed this:We are working with a customer[presumably TSMC] towards a mid-node insertion of EUV at the 10nm logic node expected in late 2016. Other customers are preparing for initial learning in a manufacturing environment.


    The next big problem has been mask contamination. The masks for EUV are reflective mirrors (actually not even all that reflective, ordinary mirrors absorb EUV just like almost anything). Without a pellicle, a thin covering for the mask, any contamination on the mask is in the focal plane and will print (see the above diagram). So masks need to be cleaned but there are a limited number of times a mask can be cleaned before the pattern starts to degrade. Intel has already said that they don’t see how to use EUV for volume manufacturing without a pellicle.


    The challenge with a pellicle is that any material absorbs EUV with pSi being the best material by far. ASML said that they will manufacture pellicles too, so presumably striking that problem off the list.


    I don’t know if progress has been made on the mask defect issue. The masks (and the mirrors in the optical path) are actually built up with multiple layers of Mo/Si. One of the challenges is that defects on the base layer can be too small to see with optical inspection (plus the size makes it equivalent to searching for a golfball in the whole of California). However, when the multi-layer mirror is build up the defect gets magnified to the point that it will print. There has been some work done on aligning the pattern on the mask so the defects are under the pattern, so irrelevant, but I’ve not seen anything about it recently. Anyway, I think mask inspection and mitigation are still an open issue.


    More articles by Paul McLellan…

    Posted on

    TSMC Sees More Growth in 2015!

    TSMC Sees More Growth in 2015!
    by Daniel Nenni on 12-06-2014 at 8:00 pm
    Categories: Foundries, TSMC

    As I wait for my plane to Taiwan I’m wondering what the New Year has in store for the fabless semiconductor ecosystem. Good things I hope but to make sure let’s take another look at one of my trusted economic bellwethers (TSMC) which I’m guessing will break the $25B revenue mark this year. That is more than a 25% growth rate year over year. What an amazing road this company has paved for us!

    Here are some interesting snippets from the TSMC 14th Annual Supply Chain Management Forum held in Hschinsu last week:

    • Next year the global semiconductor industry will grow 4%-5%
    • We do not foresee any unusual inventory supply chain adjustment
    • The global foundry industry is expected to expand 12% in revenue next year from this year
    • TSMC’s foundry market share will rise to 53% of the global market this year, compared with 49% last year
    • 20 nanometer chips will account for 20% of the firm’s total revenue this quarter
    • Revenue from 20nm chips should be more than double next year
    • TSMC is scheduled to begin pilot production of its advanced 10nm technology in Q4 2014 and to ramp up production at the end of 2016
    • Manufacturing capacity will increase by 12% from last year, with total annual capacity expected to reach 8.2 million 12-inch equivalent wafers in 2014

    “TSMC’s success comes from collaborating with our customers and suppliers through our Grand Alliance so that we magnify each others’ innovations and stand together as a most powerful competitive force in the semiconductor industry,” said TSMC Co-Chief Executive Officer Dr. Mark Liu. “Our supplier partners are a critical part of this alliance, and we look forward to reaping the rewards of many years of strong growth together.”

    The Outstanding Contribution Award went to Applied Materials for EPI/PVD Equipment and Local Service. From what I heard this is in direct response to the success of the 16FF+ process but more on that later.

    One of the things I have enjoyed over the years is the candid nature of Morris Chang’s comments. Even on the quarterly conference calls which are usually scripted. So far I have experienced the same from heir apparent Mark Lui. Take a look at Mark’s resume on the TSMC website:

    Dr. Mark Liu is currently President and Co-Chief Executive Officer at Taiwan Semiconductor Manufacturing Company (TSMC). Prior to this, he was Co-Chief Operating Officer from March 2012 to November 2013. Before that, he was Senior Vice President of Operations from 2009 to 2012. From 2006 to 2009, he was a Senior Vice President responsible for the Advanced Technology Business at TSMC. From 1999 to 2000, he was the President of Worldwide Semiconductor Manufacturing Company.

    Prior to joining TSMC, from 1987 to 1993, he was with AT&T Bell Laboratory, Holmdel, NJ, as a research manager for the High Speed Electronics Research Laboratory, working on optical fiber communication systems. From 1983 to 1987, he was a process integration manager of CMOS technology development at Intel Corporation, Santa Clara, CA, developing silicon process technologies for Intel microprocessor.

    Ph.D., Electrical Engineering and Computer Science, University of California, Berkeley

    Some people say filling the shoes of Morris Chang will be difficult but I do not see a problem here. I would hold Mark’s credentials up against any other CEO in the semiconductor industry, absolutely.

    Also Read: Intel is NOT Quitting Mobile!

    Posted on

    What makes the world smart?

    What makes the world smart?
    by Pawan Fangaria on 11-25-2014 at 4:00 pm
    Categories: Coventor, EDA, Foundries, TSMC

    The simple answer is when everything in the world is smart. But if you think deeply, you would find that the continuous progression to make things easy in life is what makes the world smarter day-by-day – the sky is the limit. In the world of computing, consider the 17[SUP]th[/SUP] century era when humanbrain was used as a computer and it took ~200 years when in 19[SUP]th[/SUP] century the first mechanical computer was invented by Charles Babbage considered as father of the computer. Today we are in much advanced state and the pace of innovation is pretty fast. Technology definitely makes things smarter, life easier, and pace of doing things faster.

    Today we are talking about IoT which makes all devices around us smart enough to sense and act as programmed by us, whenever and from wherever we want. What makes it possible? Sensor is not a synonym of smart, but it is the technology which enables smart things to be done. Various types of sensors can detect every movement, temperature, pressure, light etc. and activate its device to do something. We often hear talk of a world with a ‘Trillion Sensors’ associated with IoT, and we are getting there….

    In 2014 MEC(MIG’s MEMS Executive Congress), Chris Wasden, Executive Director, Sorenson Center for Discovery and Innovation, University of Utah talked about the number of internet devices in use: >5 Billion today and is expected to reach 18B by 2018, and the number of sensors crossing 1 Trillion by 2025. And he talked about platform leaders (device, chip, MEMS etc.) to emerge and MEMS to co-create an industry platform to reach the 1T target.

    Interestingly, foundry leaders are taking great interest in MEMS. George Liu, Director, TSMCtalked about multiple technology drivers (Personal, Home, City, Automotive and so on) in the context of IoT as against mainly computers in last several decades. He recognized the importance of sensors in making the devices intelligent and smart and also the gaps (material, architecture, low power, integration, packaging, capacity and price) that need to be filled to bring MEMS into main stream. And how can foundry contribute in filling the gap? Of course supply chain, ROI, scaling and so on, but what caught my attention are sensor and MEMS PDKs and joint process & product development between design and foundry. Wow! This can open up big opportunity for fabless MEMS development. This reminds me about one of my blogs (What will drive MEMS to drive I-o-T and I-o-P?) in which there was emphasis on standardization which can bring MEMS into volume production, and GLOBALFOUNDRIES pursuing the path of IC fab-like production discipline for MEMS.

    Getting to 1T sensors is not a slam dunk; like EDA enabled fabless IC development, we need highly sophisticated and integrated automation including modeling to accelerate MEMS development. In the days to come we will see newer and newer MEMS devices, which is beyond our imagination today. But that reality has to be complemented by automated tools which can model the MEMS accurately, integrate them at system or IC level and verify accurately as fast as possible.

    Taking at look David Cook’sblogat Coventorwebsite where he mentions about CoventorWare and MEMS+for MEMS+IC co-design, modeling, simulation and analysis, and SEMulator3Dfor virtual fabrication of MEMS devices to cut down on long build-and-test cycles through fab and improve yield before production, I concur with him that these tools are very apt in today’s environment to cater to the complexity of a variety of MEMS, yet meet the shrinking time-to-market window. In fact this reminds me about another blog written by Gunar Lorenz on new capabilities in MEMS+ 5.0– Breakthrough MEMS Models for System and IC Designers.

    In MEMS+ 5.0, Reduced Order Models (ROMs) of MEMS devices (which allows writing out snap shots of sophisticated nonlinear multi-physics models into Verilog-A protecting the IP) can be exported into Simulink schematics for system designers and circuit schematics for IC designers. Verilog-A ROMs can run up to 100 times faster than full MEMS+ models in CadenceVirtuoso or MATLABSimulink. Users can decide whether to write out ROMs in Verilog-A for circuit schematic or MROM (a new file format) for Simulink. The environment provides good set of controls for users to tradeoff between accuracy and speed. Simulation results from MROMs can be viewed and animated in 3D, just like results from full MEMS+ models.

    Smart tools to develop smart MEMS, smart MEMS to develop smart devices and smart devices to make smart eco-system are must to create a smart world!

    More Articles by Pawan Fangaria…..

    Posted on

    Intel 2014 Investor Meeting and 14nm Status

    Intel 2014 Investor Meeting and 14nm Status
    by Scotten Jones on 11-21-2014 at 6:30 pm
    Categories: Foundries, Intel Foundry, TSMC

    Intel’s investor meeting was held yesterday and for me the presentation that is most interesting is Bill Holt’s. The presentations are available on the Intel website: Intel Corporation – Presentations Material 2014. Here is the 2013 version of this presentation: Intel Corporation – Presentations Materials 2013. First off I want to vent a little, what is up with the European paper size? Does Intel have a secret plan to get everyone in the US to buy new printers?

    On slides 3, 4 and 5, the 14nm yields are shown versus 22nm. The good news for Intel is the yields are finally looking pretty good; the bad news is it has taken a long time to get there. I find it interesting that TSMC is reportedly already getting good yields on their 16nm process suggesting their 16nm/14nm development has proceeded more smoothly than Intel’s. From what I have heard Samsung and Global Foundries continue to struggle with 14nm yields.

    On slide 7, 14nm pitches of 42nm for STI, 70nm for gate (GP) and 52nm for M1 (M1P) are presented. This is in contrast to TSMC’s pitches of 48nm for STI, 90nm for GP and 64nm for M1P as reported at IEDM 2013. This gives a GP x M1P of 3,640nm[SUP]2[/SUP] for Intel and 5,760nm[SUP]2[/SUP] for TSMC. I have two observations on this:

    [LIST=1]

  • This is comparing Intel’s 14nm to TSMC 16FF. At the 2014 IEDM on December 15, 2014 TSMC is scheduled to present what looks to be 16FF+. It will be interesting to see what if any pitch improvements they report for 16FF+ versus 16FF and how that compares to Intel. The TSMC 16FF GP and M1P are the same as 20SOC, at the 2014 TSMC technology symposium 16FF+ was reported to offer a 15% improvement over 20SOC so perhaps GP x M1P is something like 4,896. I should note here that I have had someone who should know what they are talking about tells me the 16FF+ does not improve density versus 16FF.
  • The BEOL pitches for Intel’s 14nm process have started to come out. My understanding is there are 8 layers of 52nm pitch metal produced with Self Aligned Double Patterning (SADP) followed by 80nm and 160nm pitch layers with air gaps and finally 3 layers of presumably large pitch metal. The use of SADP for the first 8 metal layers means they are 1D metal layers and the design rules are very restrictive. It seems unlikely to me that a foundry could get away with such restrictive rules and this is a key part of why Intel can produce smaller metal pitches than anyone else (more on the metal layers later).

    Slide 8 shows a 0.54x scaling in SRAM size, an impressive achievement!

    Slides 9 through 14 present fin scaling and show scaling to a smaller pitch while simultaneously increasing the fin height. This is another impressive achievement.

    Slide 15 presents Intel’s leadership in introducing new process technologies to the industry. Once again these achievements are impressive and it illustrates how much Intel has helped to drive the industry forward over the last decade. The key question this slide doesn’t address is what is next and will Intel maintain a lead. TSMC, Samsung and Global Foundries are all ramping up their FinFET processes and have essentially “caught up” on that innovation. In my opinion the next innovation will be Germanium or Indium Gallium Arsenide fins and it will be interesting to see who get there first.

    Slides 18 and 19 present the 14nm Interconnect. I have to say I am very surprised by the 13 layers of interconnect at 14nm (the number of metal layers isn’t listed here and is from other sources). Intel had 6 metal layers for 180nm and 130nm while transitioning from aluminum to copper metallization; at 90nm they had 7 metal layers, 8 metal layers at 65nm and then 9 metal layers at 45nm, 32nm and 22nm. My expectation at 14nm was 10 metal layers. What I think happened was the use of SADP to produce the 52nm critical metal pitches forced 1D metal and a lot of metal layers to accomplish the required interconnect. My “guess’ is:

    • M1 through M8 are alternating x and y direction metal layers all serving for short signal runs.
    • M9 and M10 reportedly have air gaps and presumably these are longer signal runs where the air gaps are need to lower the RC delay.
    • M11, M12 and M13 are presumably large pitch metal runs for power and ground.

    Slide 20 is a new version of the “infamous” slide showing Intel’s density lead. In the past the x-axis has been node but has now been switched to time. Now instead of Intel lagging and then pulling ahead they consistently lead. The following is my own version of this slide comparing Intel and TSMC actual processes and then forecasting TSMC 16FF+ with a 15% shrink and 10nm with a 2.2 density improvement based on the TSMC technology symposium early guidance (these are updated projection since my “Who will lead at 10nm post”). For Intel I used my own trend projected 10nm numbers.

    Intel Versus TSMC GP x M1P by year of technology introduction.

    As can be seen from this plot, Intel consistently leads for density; the problem to me with this analysis is until recently Intel was exclusively using their processes for microprocessors (MPU) which have a much narrower set of performance requirements than processes for foundry use. Intel only had to focus on fast transistors while TSMC has to provide processes that meet a wide variety of different requirements. At 22nm Intel’s MPU and foundry processes have the same pitches for GP and M1P but will that hold at 14nm and if so how many customers will accept the restrictive design rules required for SADP metal layers?

    Slides 22 and 23 show Moore’s law is alive and well at least at Intel. The cost per wafer goes up with each generation but the die shrinks more than make up for it. As we have entered the multi-patterning era wafer costs are rising faster than we have historically seen but at least at Intel the die shrinks are overcoming this.

    Some observers believe that at the foundries the increase in wafer cost at 20nm due to multi-patterning has overwhelmed the die shrink and die costs have risen. I do not believe this but rather think the die cost reductions have slowed. At the 16nm/14nm node at foundries the wafer costs will again increase (although the use of 20nm backend pitches mitigates this to some extent) and the shrinks are minimal. At 16nm/14nm die cost reductions will be minimal at best. At 10nm I expect foundries to deliver competitive cost per die reductions as we get back to full shrinks, in fact TSMC has guided a 2.2x increase in density. Wafer costs from 16nm to 10nm at TSMC are not going to go up anywhere near 2.2x!

    All in all Intel continues to deliver impressive technological progress and do it economically. Comparing Intel with TSMC (or any foundry) for device area is really not a valid comparison until Intel is a substantial foundry player and the processes being compared are both being used in the foundry space.

    I am still going through all of the presentations but I also wanted to comment on Stacy Smith’s presentation slide 51 which shows Intel’s fab capacity and demand coming back into balance, which is a really big deal after the low levels of loading seen in 2012 and 2013.

    • Posted on

    Who is REALLY Using TSMC 16FF+?

    Who is REALLY Using TSMC 16FF+?
    by Daniel Nenni on 11-12-2014 at 7:00 am
    Categories: FinFET, Foundries, TSMC

    As I wrote last week there is a whole list of companies on LinkedIn with people working on TSMC 16nm. Today TSMC released a list of customers that have risk production 16FF+ silicon. Most of us knew this already but now we can talk about it in more detail. This is a really big deal for the FinFET doubters out there. Just because Intel had all sorts of yield trouble with 14nm does NOT mean that TSMC will experience the same type of issues.

    Also Read: Who is Using Samsung 14nm?

    According to TSMC the 16FF+ process provides 40% more performance than 20nm or consumes 50% less power at the same speed. The first applications you will see of course are mobile, specifically stated is “high-end mobile” meaning that 16FF+ is much faster than Samsung 14nm. Computing, networking, and consumer applications are also mentioned.

    Also Read: Let the FinFET Yield Controversy Begin!

    As an example of high performance a 2.3GHz ARM Cortex®-A57 is referenced and for low power a 75mW Cortex-A53. Yield is also mentioned as being ahead of the curve in comparison of all the other TSMC nodes. Remember TSMC used the same metals for 16nm as it did for 20nm which in hindsight was simply brilliant. Solve the double patterning riddle first then add FinFETs and address the added fin variation challenges.

    Also Read:Cliff Hou at TSMC OIP

    As Cliff Hou mentioned in his keynote at last month’s TSMC OIP Forum, a wide variety of EDA tools and hundreds of process design kits with more than 100 IPs, all of which have been silicon validated, is already supported for 16nm. TSMC also stated that 16FF+ has close to 60 customer designs scheduled to tape out by the end of 2015. Coincidentally, high volume 16FF+ ramp should start in Q3 2015, just in time for the next Apple iPad refresh.

    “Our successful ramp-up in 20SoC has blazed a trail for 16FF and 16FF+, allowing us to rapidly offer a highly competitive technology to achieve maximum value for customers’ products,” said TSMC President and Co-CEO, Dr. Mark Liu. “We believe this new process can provide our customers the right balance between performance and cost so they can best meet their design requirements and time-to-market goals.

    “TSMC 16FF+ process technology enables Avago to design highly optimized custom silicon solutions for networking applications in cloud datacenters and enterprise networks,” said Hock Tan, President and CEO of Avago Technologies Limited. “TSMC’s 16FF+ process technology in combination with Avago’s industry leading SerDes, memory, processor cores, and design implementation techniques deliver unparalleled time-to-market, performance and power benefits to OEM customers.”

    “Sixteen-nanometer FinFET Plus technology provides compelling performance per watt advantages, enabling a myriad wave of market inflection points such as Internet of Things, 5G networks and software defined networks,” said Tom Deitrich, Senior Vice President and General Manager for Freescale‘s Digital Networking group. “Powering the new virtualized network, a new family of Layerscape™ multicore processors using ARM® and Power Architecture® technologies will be Freescale’s first offerings to leverage this innovative process technology.”

    “Our collaboration with TSMC on 16FF+ technology will give LG strong competitiveness with respect to power, performance and area in the mobile AP market,” said Bo-ik Sohn, Senior Vice President at LG Electronics. “We believe that the product made through our partnership with TSMC will meet the widespread consumer demand for distinctive mobile technology.”

    “TSMC is a trusted technology partner, helping to drive MediaTek’s success over the past decade to deliver market leading SoCs,” said CJ Hsieh, President of MediaTek. “With TSMC’s first ever FinFET 3D architecture and enhanced plus version, MediaTek advances mobile and home entertainment SoCs demonstrating even faster speed, optimized power and reduced chip size. The performance boosts and power reduction for MediaTek’s processors and modem technologies, compared to previous generations, has proven TSMC’s 16FF+ to be a highly competitive process technology for our chipsets.”

    “NVIDIA and TSMC have collaborated for more than 15 years to deliver complex GPU architectures on state-of-the-art process nodes,” said Jeff Fisher, Senior Vice President, GeForce Business Unit, NVIDIA. “Our partnership has delivered well over a billion GPUs that are deployed in everything from automobiles to supercomputers. Through working together on the next-generation 16nm FinFET process, we look forward to delivering industry-leading performance and power efficiency with future GPUs and SOCs.”

    “Our partnership with TSMC enables us to address evolving semiconductor technologies and to provide state-of-the-art solutions for our customers in the automotive, industrial and ICT fields,” said Hisao Sakuta, Chairman & CEO of RenesasElectronics Corporation. “Now, we want to take full advantage of the 16FF+ technology to deliver added values for our customers in the advanced automotive information and ICT markets.”

    “TSMC is once again demonstrating their leadership in the industry by delivering their 16FF+ process with exceptional results,” said Moshe Gavrielov, President and CEO of Xilinx. “This risk production milestone achievement and our continued close collaboration is enabling Xilinx to realize the industry’s highest FPGA performance per watt and an unprecedented level of programmable systems integration with the industry’s first All Programmable MPSoC and 3rd Generation 3D ICs.”

    About TSMC
    TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company’s owned capacity in 2014 is expected to be about 8.2 million (12-inch equivalent) wafers, including capacity from three advanced 12-inch GIGAFAB™ facilities, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC China. TSMC is the first foundry to provide both 20nm and 16nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.

    More Articles by Daniel Nenni…..

    Posted on

    Money for data and your MEMS for free

    Money for data and your MEMS for free
    by Don Dingee on 11-10-2014 at 12:00 am
    Categories: Foundries, TSMC

    An ongoing IoT debate centers on the notion that just because we can do something does not mean we should. From discussions at the recent MEMS Executive Congress, looking at what TSMC and some others see as the endgame for a trillion sensors signals possible trouble ahead. Continue reading “Money for data and your MEMS for free”