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IoT Sensor Node Designs Call for Highly Integrated Flows

IoT Sensor Node Designs Call for Highly Integrated Flows
by Tom Simon on 02-21-2015 at 7:00 pm
Categories: Arm, Cadence, Coventor, EDA, IoT, Mobile, TSMC

Applications for IoT sensors are becoming more sophisticated, especially for industrial usage. Building optimal sensors for different applications requires multi-domain design, optimization and verification flows. The sensor devices are usually MEMS, and as such have electrical properties that need to be tailored to the analog circuitry they are connected to. Many MEMS devices are not completely passive: they often have drive systems to keep them in their most linear range of operation. For example an accelerometer will have two comb capacitors, one is for sensing, the other is to control the proof mass.

Cadence, Coventor and ARM recently held a webinar that showed how many important considerations in designing an industrial IoT sensor node can be addressed. The full session is available here.

In these designs the analog circuity needs to be designed and optimized at the same time as the MEMS structures. Chris Welham, Worldwide Applications Engineering Manager at Coventor, points out in the webinar that Coventor offers their MEMS+ product as a vehicle for building 3D design of MEMS elements in conjunction with circuit design tools. The key to making this effective is that after the MEMS designer creates a device, they can export it to Cadence, where it is represented as a parametric simulation model, symbol and PCell. The parameters exposed to the circuit designer are specified when the MEMS+ model is generated. This means that the circuit designer can alter specific parameters of the MEMS device easily and independently. In the webinar Cadence showed how Virtuoso ADE GXL can be used to concurrently optimize the circuit and MEMS parameters to meet the system design spec. The PCell that is produced by MEMS+ produces the necessary layout for mask generation.

IoT sensors need to be compact, rugged and have battery life considerations. These needs often drive the specific packaging configuration for the various SOC’s and MEMS chips in the unit. Designers can utilize BGA, bond wires and TSV’s in an assortment of configurations that can include stacked die with silicon interposer. In the webinar Ian Dennison, Solutions Group Director at Cadence, shows examples of each of the 3D-IC approach alternatives and highlights design and verification aspects of each.

For designs with bond wires, stacked die present special challenges. Manufacturing and coupling noise considerations play a major role in wire placement and shape. Cadence SIP allows wire profiles to be defined and then viewed in 3D. The webinar showed several examples where wire profiles need to be configured to provide adequate clearances to avoid things like overhanging shelves or neighboring wires.

TSV’s offer many advantages over bond wires, but working with them adds complexity to the chip design process. First off, on the plus side, TSV’s reduce overall system cost. On-chip they save routing resources that would otherwise be needed to get signals to the chip boundary and they lower parasitic capacitance and inductance. However the chip floorplan must account for their location. In the webinar Cadence discussed how Encounter and Virtuoso let designers work with TSV’s.

Tim Menasveta, CPU Product Manager at ARM went last but covered the critical aspects of how creating a sensor hub in the IoT sendor device can help the IoT senor meet its many design requirements. Without a hub, all the raw sensors would be transmitting to the aggregation point continuously. This wastes power and bandwidth. Instead with a local processor the IoT sensor node can decide when and what data should be sent. Additionally sensor fusion is extremely important. Many of us are familiar with the necessity of combining the raw inputs from a gyroscope and accelerometer to obtain accurate real world results. Also temperature is an important input for most sensor interpretation. Sensor fusion is useful for dealing vibration or effects of nearby iron objects when calibrating a compass.

The new Cortex-M7 boasts an improved DSP and floating point unit when compared to its predecessor the Cortex-M4. The M7 is ideal for bare metal code. The M8 is more suitable for higher level OS’s. There is also an optional double precision floating point unit available for the M7. To facilitate development of designs using the Cortex-M7, Cadence and ARM have collaborated on an implementation reference methodology built on TSMC’s 40LP process. This design uses Physical IP by the ARM Physical IP Division. It is a low power design that has support for power gating.

The webinar pulled together a wide range of technology, all of which is necessary for putting together leading edge IoT sensor based designs. For a more in depth review of the technology,I suggest following the link at viewing it.

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TSMC 20nm Essentially Worthless?

TSMC 20nm Essentially Worthless?
by Daniel Nenni on 02-15-2015 at 7:00 am
Categories: Foundries, TSMC

It happens at every process node, professional journalists write that something is broken and blames TSMC like a worn out record. To be fair they are not semiconductor professionals with access to the fabless semiconductor rank and file and are easily manipulated which is what happened again at 20nm. Remember when NVIDIA suggested that TSMC 20nm was economically challenged? And the media changed that to “essentially worthless?” Thankfully Apple knew better otherwise we would not have the amazing iProducts we have in our hands today.

Nvidia deeply unhappy with TSMC, claims 20nm essentially worthless
By Joel Hruska on 3/23/2012

Back at 40nm I was the foundry liaison for an IP company and the GPU part of AMD was a big customer. I was the executive sponsor for AMD meaning that whenever there was an escalated problem it landed on my desk. And there were ALWAYS escalated problems at the bleeding edge of GPU design, absolutely.

As 40nm was ramping NVIDIA came out and said their GPUs would be delayed because of yield problems and they pointed fingers at TSMC. The media jumped all over this of course but the AMD guys and I had a good laugh because AMD did not have the same yield problems. At 40nm they had these things called “recommended design rules” (RDRs) to increase yield. One of them was doubling the vias in case there was a one in a billion failure. Of course this increased area and capacitance so the clever NVIDA designers did not do it and had billions of single vias. AMD on the other hand respected the RDRs and beat NVIDIA to 40nm. When the dust settled NVIDIA did admit to design related yield issues but that was not front page news of course.

The same thing happened at 28nm when the fabless guys talked about wafer shortages on conference calls as an excuse for not making their Wall Street targets. The media immediately played the yield card and threw TSMC under the bus. Come to find out TSMC built 28nm capacity based on customer forecasts which were half of what they should have been. TSMC ended up with 100% market share at 28nm versus the 50% forecast and the rest is history.

Nvidia Blames TSMC’s 28nm Process Technology for Slow Sales
by Anton Shilovon 05/11/2012

In March of 2012 NVIDIA came out saying 20nm was not economically feasible and blamed TSMC. In fact, NVIDIA made a detailed presentation at the International Trade Press Conference. The media was all over it reporting in detail WHAT was said but not once considered WHY it was being said and WHY at that particular venue. The entire fabless semiconductor ecosystem had a good laugh because silicon doesn’t lie like people do and the last laugh would be ours.

Some points to ponder:
[LIST=1]

  • Why was this presented at a press conference versus a technical conference?
  • The NVIDIA CEO and TSMC CEO are very close friends, right?
  • The media says GPUs will skip 20nm for 16nm
  • 16nm is really 20nm with low power FinFETs, right?
  • NVIDIA has a 20nm Tegra SoC in production
  • Apple has two 20nm SoCs in production
  • Oracle has a 20nm high performance CPU in production
  • Xilinx has 20nm FPGAs in production

    So tell me, what really happened to the 20nm GPUs?

    Disclaimer: This is written from my aging memory so correct me if I’m wrong here…

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    Do You Need a Silicon Catalyst?

    Do You Need a Silicon Catalyst?
    by Daniel Nenni on 02-14-2015 at 7:00 pm
    Categories: EDA, Foundries, IP, Synopsys, TSMC

    Lately there has been significant concern over the rising costs of designing in silicon and the troubling decline in venture investments in semiconductors. These alarming trends include fewer IPOs, a falloff in the amount and frequency of early stage seed investments, and comparatively low industry organic growth rates. A new company called Silicon Catalyst has recently been formed to address some of the key challenges facing entrepreneurs attempting to innovate in semiconductors … namely the challenge of raising sufficient funding and obtaining the appropriate design, prototyping, and test capabilities to move from concept to working prototypes.

    While there are other incubators for software and some for hardware, Silicon Catalyst looks to be the first focused exclusively on startups creating solutions in silicon. Co-founded by three semiconductor veterans: Mike Noonen, Rick Lazansky and Daniel Armbrust, the incubator announced its initial partners last month. They are industry leaders Synopsys, TSMC and Keysight (formerly Agilent) who will provide design tools, fabrication and test capabilities respectively.

    “The launch of this startup incubator parallels TSMC’s emphasis on a ‘Grand Alliance’ of collaborating companies in the semiconductor industry to increase innovation,” said Rick Cassidy, President, TSMC North America. “TSMC is pleased to join the efforts of Silicon Catalyst to help the next wave of fabless semiconductor start-ups achieve success.”

    “A vibrant start-up community is a valuable component in the development of any business and the multi-trillion-dollar industries that we enable,” commented Aart de Geus, Chairman and co-CEO, Synopsys. “Synopsys is proud to be a Silicon Catalyst founding partner to support semiconductor solution start-ups.”

    The Silicon Catalyst incubator’s initial location in Silicon Valley is expected to be announced shortly. Startups are expected to come from universities, industry entrepreneurs and spinouts not just in Silicon Valley but from all around the world. Silicon Catalyst plans to collaborate with local incubators to enable these entrepreneurs to leverage the Silicon Catalyst partner resources without needing to relocate. The first round of screening is expected to begin within the next two months.

    Silicon Catalyst is engaged in discussions with many industry strategic partners who are expected to help select, guide, invest in and be potential acquirers once the startups graduate from the incubator (over a maximum of 24 months). In addition to some modest funding of up to $500k and providing access to the essential services needed for new designs, Silicon Catalyst intends to pair each startup with an experienced mentor who can provide relevant advice and assistance which is viewed as essential to address the challenges that these early stage companies inevitably encounter.

    Investors are mostly ignoring early stage semiconductor investments, however Silicon Catalyst and its partners believe we are entering a long term wave of innovation that requires new semiconductor innovation at their core to address opportunities in IoT, biotech, energy, transportation and mobile. Inspiration for an improved business incubation model and an accompanying vibrant startup community came from the biotech and pharmaceuticals industries that have found ways to address the high upfront costs of device and drug development. Since upfront costs are significantly reduced, start-ups are expected to become much better investments since funding can go directly to innovation and value creation. Silicon Catalyst expects to see renewed interest over time from angel, strategic, and venture investors as a result.

    It will be interesting to see how the semiconductor industry embraces and supports this new model. Optimistically, with sufficient backing, we will look back on this as an important part of today’s fabless semiconductor ecosystem, absolutely.

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    TSMC’s OIP: Everything You Need for 16FF+ SoCs

    TSMC’s OIP: Everything You Need for 16FF+ SoCs
    by Paul McLellan on 02-13-2015 at 7:00 am
    Categories: FinFET, Foundries, TSMC

    Doing a modern SoC design is all about assembling IP and adding a small amount of unique IC design for differentiation (plus, usually, lots of software). If you re designing in a mature process then there is not a lot of difficulty finding IP for almost anything. But if you are designing in a process that has not yet reached high-volume manufacturing (HVM) then there is a new set of challenges. If you are really on the bleeding edge and the volumes are going to justify the cost, then the company has to design its own IP since commercial IP just is not available (think companies like Qualcomm or Apple). For everyone else, they need to wait for a broad portfolio of IP to be available. But they don’t want to wait forever. TSMC has its OIP program to ensure that IP is available as soon as possible, that it is tested in silicon and generally is getting ahead of the curve. After all, TSMC makes money when designs go into production and the critical path for getting a design into production goes right through the middle of having EDA tool flows and IP available.TSMC’s IP ecosystem surpassed the mark of 8,000 registered IPs in 2014, from more than 40 IP partners. TSMC IP Alliance partners, together with TSMC internal IP teams, form the largest and fully qualified IP platform available to IC designers in the world. It is a live ecosystem, constantly evolving to adapt to customer needs. With the new creation of ULP processes targeted to IoT applications, a more comprehensive solution is now necessary. TSMC 3rd party IP vendors will add their expertise, creating updated and new low-power IP for TSMC processes.Last year’s Open Innovation Platform 2014 (OIP) Ecosystem Forum was held in September. Over 1000 customers and partners participated. The main focus was on TSMC’s latest processes, in particular 16FF+. TSMC and its partners made the following announcements:

    • OIP has provided over 12 years of ecosytem enablement
    • a new 28nm 28HPC high performance process offering available
    • 20nm in mass production
    • 16FF+ ready for product design
    • Reference flows for 16FF+ delivered
    • ARM big.LITTLE vaiidated in 16FF+
    • 10FF EDA tools ready for early customer design starts

    At the forum, the TSMC OIP Partner of the Year Awards were announced. First for IP:

    • Foundation IP: ARM
    • Interface IP: Synopsys
    • Analog/Mixed-Signal IP: Analog Bits
    • Embedded Memory IP: eMemory Technology
    • Emerging IP Company: Silicon Creations
    • Specialty IP: Dophin Integration
    • Soft IP: Cadence

    Then the EDA awards for the joint development of the 16FF+ design infrastructure (alphabetical):

    • Apache business unit of ANSYS
    • AtopTech
    • Cadence
    • Mentor
    • Synopsys

    The key to the diagram above is purple is Synopsys, red is Cadence, green is Mentor (I think of blue being Mentor based on their website), yellow is Apache, blue is Atoptech and pink is Invarian.These tools go to create a digital SoC (synthesis, place & route) reference flow that captializes on 16FF+ PPA through optimized tool and standard cell implementation, with a constraint variation model for accurate timing signoff, a self-heating model to address thermal concerns, rush current analysis for powering blocks down and up, and more. They also create a customer reference flow for custom digital and analog/mixed-signal with a complete “number of fins” methodology to replace length/width of planar processes. The flow takes into account layout dependent effects, voltage dependent rule checks and a full transistor-level electromigration (EM) and IR drop analysis flow for power analysis.The release of new ultra-low-power (ULP) processes at mature nodes to support the upcoming IoT opportunities, does not lower the focus of TSMC on wide set of Foundation, Interface and Soft-IP from both TSMC and its IP Alliance partners for the leading edge.

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    TSMC vs Samsung!

    TSMC vs Samsung!
    by Daniel Nenni on 02-10-2015 at 9:30 pm
    Categories: Foundries, TSMC

    One of the trending topics in Taiwan last week is the escalating conflict between Samsung and TSMC. This time however it is of a legal nature which has been a long time coming for the semiconductor industry. Reverse engineering has been an integral part of the semiconductor business since the beginning, as has intellectual property theft. The difference being employees with prior knowledge are doing the reverse engineering and the resulting email trails are their undoing every time.

    The driving force behind this of course is the demand for second source foundry manufacturing. As I have mentioned before, at 40nm and above TSMC design databases (GDS II) were given to UMC, Chartered, and SMIC for second, third, and sometimes fourth source production. At 28nm and 20nm it is much more difficult to do and at 14/16nm and 10nm it will require a copy exact strategy or a significant redesign. In fact, at 10nm you will not even be able to use the same design team for different foundries due to strict legal constraints.

    Take a look at this blog about the legal action TSMC took against SMIC at 180nm and 130nm. It is an interesting story, one that will certainly have some commonality with the Samsung legal action:

    TSMC versus SMIC
    byDaniel Nenni
    Published on 09-28-2009

    The recent events surrounding the TSMC vs Sasmung legal action are detailed in this article. Please note that I have not fully fact checked this yet but will do so in the coming weeks. You should also know that this is a Taiwanese publication known for “Solid, sober reporting, CommonWealth magazine gives Taiwan’s entrepreneurs and decision-makers the insights they need to keep ahead…”

    Hunting Down a Turncoat
    By Liang-Rong Chen
    Published: January 23, 2015

    It really is a sordid story if you have the time and interest. The bottom line, as with the SMIC case, is that it alleges Samsung hastened the delivery of 14nm by using technology that they obtained from a former TSMC executive. Right now the legal action is against the former employee but that may change when the Samsung 14nm silicon is fully investigated.

    “The 16nm and 14nm FinFet products that both companies will mass produce this year were even more alike. It could be hard to tell (if the product) came from Samsung or TSMC if only structural analysis is used, the report said.”

    One of my former employers had a similar experience when a consultant “borrowed” code from a competitor to hasten a product delivery. The result was hundreds of millions of dollars in damages, jail time, and a forced acquisition. At one time I remember customers using the software in question were also under legal threat but fortunately cooler heads prevailed. It really is a bad idea to take legal action against customers.

    The FinFET technology at the heart of today’s fierce battle between TSMC and Samsung was also one of Liang’s strengths. In its claim against Liang, TSMC stressed: “Liang Mong-song was deeply involved in TSMC’s FinFET process research, and he was the inventor behind related patents.”

    According to Patent Buddy, 47 patents were filed and 15 issued between June 2001 and July 2012:

    Mong-Song Liang Inventor – TSMC Patent Owner

    I would be interested to know which of these patents are FinFET related if someone out there has the time, expertise, and interest to investigate. Hopefully the result of this blog will be a lively conversation in the comments section, just remember that this is but one side of a very complicated story.

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    Has the Semiconductor Industry Gone Mad?

    Has the Semiconductor Industry Gone Mad?
    by Daniel Nenni on 02-07-2015 at 7:00 pm
    Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

    The weather in Taiwan last week was very strange. It was so cold I tried to turn on the heat in my hotel room only to find out it was not possible. If you want more heat they bring a portable heater because who needs central heat in Hsinchu? Even stranger is all of the media hyperbole on the next process nodes:

    Intel CFO: We’re so far ahead that Apple has no choice but to work with us

    What he actually said is that Intel is so far ahead of the competition when it comes to PC processors that Apple (and just about every other PC maker) has no choice but to use Intel chips. True as that may be I’m not sure reminding everyone that you have a monopoly on the PC business is such a great idea. In regards to Apple it is hard to tell what they will do for semiconductors. At one time the media thought that Apple would no longer do business with their competitor (Samsung) after successfully moving to TSMC at 20nm. Now the media has “affirmed” that Apple is using Samsung 14nm exclusively for the iPhone and iPad this year:

    Apple affirmed to return to Samsung for 14nm ‘A9’ chips for next iPhones, iPads

    As I have said before, no one likes a monopoly so I find it highly unlikely that Apple will use just one foundry if at all possible moving forward. Given that they make two different chips, one for the iPhone and a larger more powerful one for the iPad, it makes using two foundries that much easier. You should also know that Samsung 14nm is LP (low power) while TSMC 16nm FF+ has a higher performance range so making the A9 at Samsung and the A9x at TSMC is much more believable.

    The other thing you should ask yourself is why did Samsung and GlobalFoundries REALLY do the 14nm licensing deal last year? The answer is because customers “suggested” they do so. And by customers I mean the two largest wafer customers which are Apple and Qualcomm of course. I remember Paul McLellan and I being briefed on this last Spring and me thinking to myself, “Has the semiconductor industry gone completely mad?”

    Samsung ♥ GLOBALFOUNDRIES

    In a recent conference call TSMC called GlobalFoundries “Samsung’s accessory” which was funny but it also has a much deeper meaning. Given the choice of a single manufacturing source for a specific process node or a source with an “accessory” Apple or Qualcomm will chose the latter, which is what they have done at 14nm. There have been no announcements as to whether Samsung and GlobalFoundries will again work together (copy exact) on 10nm but if Apple and QCOM say so they will, absolutely. You have to follow the money trail in the fabless semiconductor ecosystem for sure.

    The other question I asked myself at the end of this trip was: “Self, how long until UMC becomes TSMC’s accessory?” And if this trend catches on who will be Intel’s foundry accessory?

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    Intel to Launch 10nm Chips in Early 2017?

    Intel to Launch 10nm Chips in Early 2017?
    by Daniel Nenni on 01-31-2015 at 7:00 am
    Categories: Foundries, GlobalFoundries, TSMC

    As I have mentioned before, Intel and the foundries approach process development from different starting points. Intel is committed to Moore’s law in reducing the transistor cost by increasing the process density in a near linear fashion. The foundries on the other hand work closely with partners and customers to determine the power, performance, and area (PPA) goals of the next process node within a specific time to market (TTM). As we all know, Apple has a very specific TTM (iTTM) which will always be the priority.

    14/16nm SoCs are already in production at Intel, Samsung, GlobalFoundries, and TSMC with products due out in the second half of 2015. This will be the first time we really get an Apple-to-Apple, IDM vs Foundry comparison with the Intel Cherry Trail and Apple A9 SoCs and I’m truly excited to see the first tear down. Considering the Apple A8 had 2B+ transistors on a 89mm2 and 8.47 X 10.5mm die, one can only imagine how many transistors the 14nm SoCs will have.

    Now that 14/16nm is in production we are looking to 10nm for our next cost reduction. I really am glad we are all calling it 10nm but as you know not all 10nm processes are created equal (Who Will Lead at 10nm?). The 10nm process design kits (PDKs) are just now hitting the streets so the design challenges have just begun. The foundries are targeting the end of 2015 for the first customer tape outs which generally means production one year later. My guess is that you will see products with 10nm silicon in the second half of 2017 which means we will again be on 14/16nm for 2016. Improved versions of course, maybe 16nm FF++++ or 14nm UUULP?

    An Intel Executive recently predicted 10nm would be available in 2017 in a candid interview on GulfNews.com out of Dubai of all places:

    “We have been consistently pursuing Moore’s Law and this has been the core of our innovation for the last 40 years. The 10nm chips are expected to be launched early 2017,” said Taha Khalifa, general manager for Intel in the Middle East and North Africa region.

    Mr. Khalifa is a 24 year Intel veteran so he should certainly know. Intel has a famous tick-tock model where they follow every architecture change with a die shrink. A tick is a die shrink and a tock is a new architecture. Broadwell was a 14nm tick, Skylake will be a 14nm tock, and Cannonlake will be a 10nm tick.

    Back in the day, we used to judge microprocessors by the clock speed (megahertz), it was a badge of honor really. I remember buying a PC with a 40MHZ AMD CPU for more money than one with an Intel 33MHZ CPU. I even shamed my brother who had just bought a 33MHZ version. Computers were really like muscle cars for nerds back then. Recently an SOC friend of mine shamed me for commenting that the A8 ONLY ran at 1.4GHZ versus 2GHZ. What can I say, old habits die hard. With SoCs, the badge of honor is getting the best SYSTEM LEVEL performance, which now, thankfully, includes battery life.

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    TSMC Finishes 2014 with the Chairman on the Call!

    TSMC Finishes 2014 with the Chairman on the Call!
    by Daniel Nenni on 01-15-2015 at 9:30 pm
    Categories: Foundries, TSMC

    I’m not a financial guy, as I have mentioned before, so let me just make some comments on the technology discussed on today’s conference call. Please note that the Chairman Dr. Morris Chang was on the call which is probably why the TSM stock went up more than 8% immediately after. Of course there was plenty of good news to go along with it but having Morris on the call definitely added market confidence, my opinion.

    The biggest number I noticed was that advanced nodes made up 51% of revenues meaning 28nm and 20nm. TSMC predicted a quick 20nm ramp with Q4 2014 revenues at 20% of the total which quite a few people did not believe. Well, 20nm came in at 21% so congratulations to all who made that possible. TSMC stated quite clearly that they expect a similar ramp with 16nm this year and it is very hard to doubt that. 20nm is expected to contribute 20% of the total revenue for 2015 so it may be a much longer node than expected.

    TSMC is raising CAPEX again to about $12B which is a 25% increase. 80% of it is for advanced nodes (28nm, 20nm, 16nm, and 10nm). Intel on the other hand is reducing CAPEX from about $11B to $10B putting them third behind Samsung and TSMC. Morris reiterated that TSMC builds fabs based on customer orders unlike others who build fabs on speculation only to find them empty. Just a guess here but that is probably a reference to Intel and the empty Fab 42.

    TSMC finished the year with a 27.8% revenue growth compared to 18% in 2013. Lets call that the “Apple Factor”. Last year Morris predicted 5% growth for the semiconductor industry 10% growth for the foundry industry and said TSMC would outperform them both. Indeed. This year Mark Lui predicts that the semiconductor industry will grow 5% and foundry revenue will grow 12% with TSMC outperforming them again.

    In regards to 10nm, qualification is still scheduled for Q4 2015 with production silicon in 2017. My guess is that 10nm will be here in time for the iPhone refresh in the fall of 2017, absolutely. 10nm is going to be an interesting node but more on that later.

    28nm continues to grow due to mid to low end 4G smartphones. You can probably thank Xiaomi for that since they use 28nm Snapdragons. QCOM is an investor in Xaiomi so that will probably not change anytime soon. TSMC continues to optimize their 28nm offerings and feels that they will be able to defend their dominant position with which I agree. C.C. Wei also siad in her prepared statement that 16nm production started in Q3 2014 with meaningful revenue scheduled for Q1 2015. My guess was first 16nm revenue will be reported in Q2 2015 and based on the Q&A session I will stick with that.

    I had to see the Q&A session in print before I commented because it was probably one of the more confusing ones I have heard/read. I don’t know who transcribes these for Seeking Alpha but they could do a better job for sure. And the analysts need to do a much better job preparing. Take a look at the transcript and let me know what you think in the comments section. The question about the server market was interesting but here is my favorite exchange:

    Roland Shu     – Citibank
    Yes I think maybe I should rephrase my question —

    Morris Chang– Chairman
    Why do you have to rephrase your question all the time?

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    Update: Who will manufacture the Apple A9?

    Update: Who will manufacture the Apple A9?
    by Daniel Nenni on 01-04-2015 at 12:00 am
    Categories: Foundries, GlobalFoundries, TSMC

    Last August I presented possible scenarios for the manufacturing of the Apple A9 processor. Quite a bit has changed since then so I think it is worth revisiting. There has also been quite a lot of misinformation in the press which is now pretty much a daily thing. Attending the IEDM conference last month really was a stark difference than what “The Google” has to offer people who are looking for answers in all the wrong places. Seriously, the chasm between the two sides (semiconductor professionals and non-professionals) really is quite large.

    Also Read: Who will Manufacture Apple’s Next SoC?

    As we all know Apple has disrupted many different industries with innovative technology and aggressive business practices, the semiconductor industry included. Apple is now one of the largest and most innovative fabless semiconductor companies and becoming part of their supply chain is bringing a whole new level of competition amongst the fabless semiconductor ecosystem. Let’s start with last year’s blog Samsung ♥ GLOBALFOUNDRIES.

    You have to ask yourself why Samsung REALLY did this deal with GF? One theory, which I firmly believe, is to get the Apple SoC business back from TSMC. Apple amongst many others (myself included) really wants GF to be successful for the greater good of the pure-play foundry business. Take a look at the last paragraph I wrote:

    An interesting thing: On one side of the briefing table was Ana Hunter, Vice President of GLOBALFOUNDRIES, formerly Vice President Foundry, Samsung Semiconductors. On the other side was Kelvin Low, Senior Director, Foundry Marketing Samsung, formerly Director Product Marketing, GLOBALFOUNDRIES. It’s a small world after all.

    Ana Hunter was instrumental in the foundry relationship between Samsung and Apple so who better to bring Apple to GF? Since the GF 14nm is a copy exact version of the Samsung 14nm, Apple has two manufacturing sources for the A9. And from what I learned at IEDM, both are now yielding in time for the next iPhone launch (September 2015). The Apple A9X (higher performance version) is still slated for TSMC 16FF+. This chip will go into tablets but may also be seen in laptops and possibly a high performance version of the iPhone making it a much higher volume chip than originally expected.

    Yes I know Barron’s is still repeating that the foundries have not figured out FinFETs leaving the door wide open for Intel blah blah blah… absolute nonsense:

    “Could Intel (INTC) be in a position to be Apple’s (AAPL) savior? That intriguing bit comes from Drexel Hamilton’s chip analyst Rick Whittington, from a note on Micron. In passing, Whittington notes problems had by Taiwan Semiconductor (TSM) and Samsung Electronics (005930KS) trying to produce 3-D transistors. Intel has mastered 3-D transistors, and so, writes Whittington “btw, very good for Intel if neither Samsung or TSM can do FinFET this next year; puts them in line to supply Apple’s internal foundry needs; more likely TSM/Samsung operate FinFET under very low yield output, keeping capacity tight.”

    Yet another analyst pretending to be a semiconductor professional…..

    Again, Samsung, GlobalFoundries, and TSMC are now yielding FinFETs with high volume production starting in Q2 2015. The next versions of iPhones and iPads will be FinFET based, absolutely.

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    IEDM Advanced CMOS Technology Platform Session

    IEDM Advanced CMOS Technology Platform Session
    by Scotten Jones on 01-01-2015 at 7:00 am
    Categories: Foundries, Intel Foundry, TSMC

    First I want recognize that IEDM once again provided all of the attendees with the proceedings as soon as we arrived at the conference, in fact the proceeding included every year of IEDM back to 1955. This is how a conference should be run! Anyone who read my blog about the SPIE Advanced Lithography Conference will know how frustrating I found SPIE not making the proceeding available until months after the conference. SPIE really needs to fix that! Being able to read the papers before a session and then review them again after the session is really helpful.

    There were three papers in the Advanced CMOS Technology Platform session that really caught my attention this year.

    TSMC
    First up was TSMC presenting their 16FF+ technology. The process presented this year provides a 15% speed improvement at the same power or a 30% power improvement at the same speed versus the 16FF process presented at IEDM last year. All of the critical dimensions disclosed for this process are the same as 2013 (48nm fin, 90nm gate and 64nm M1 pitches). The level of performance improvement TSMC has achieved is more in-line with what you would see for a new node and to achieve this level of improvement while maintaining the same critical dimensions is really an achievement. Unfortunately from my perspective the paper only discussed the results and didn’t provide any details on how they were achieved other than to say they focused on reducing capacitance. Still the results are impressive!

    Intel
    The next paper that really caught my attention was the Intel paper on their 14nm technology. Intel’s 14nm technology is the densest 16nm/14nm class process currently available with 42nm fin, 70nm gate and 52nm metal pitches. The gate pitch x metal pitch metric is 0.51x the 22nm technology, IDsat is 15% better for NMOS and 41% better for PMOS. Active power is 30% better than 22nm with 10x better tddb and less Vt variation.

    Once again there wasn’t a lot of detail presented about the process but there were a few interesting disclosures:
    [LIST=1]

  • The process uses solid source doping to dope under the fins. My belief is that the STI trenches between the fins are filled with doped glass that is then etched back to the bottom of the fin and then annealed to out-diffuse the dopants. I would expect both p and n doped glasses would be required. I have come up with one integration scheme that does this without additional masks but it would result in topography at the bottom of the wells. I think it is more likely one additional mask would be needed.
  • Air gaps are used on two of the interconnect layers. Data was presented for delay improvements for metal 4 – 17% and metal 6 – 14%. Interestingly my understanding is that analysis of actual Intel products in the field has found the air gaps on layers 5 and 7. During the presentation it was also disclosed that a mask is needed for each air gap. After the paper someone asked how this is done and author declined to comment. Based on cross sections and the one mask per air gap disclosure it seems likely that this is the process Intel described in 2010.
  • I was surprised when it was first disclosed that this process has 13 metal layers. Intel used 6 metal layers at 180nm (aluminum) and 130nm (copper), 7 layers at 90nm, 8 layers at 65nm and 9 layers at 44nm, 32nm and 22nm. I was expecting 10 metal layers at 14nm. I think what has happened here is that Intel has moved to SADP for critical metals layers and SADP really only produces gridded lines and spaces for a 1D layout. This has likely required additional metal layers versus previous 2D metal layers.
  • During the presentation Intel briefly displayed the pitches for all the metal layers. Unfortunately it wasn’t up long enough for me to copy down the numbers and unlike many attendees I respect the no photography rule. The pitches are also not in the paper. I have seen measured pitches on products in the field but I can’t share them yet. I will say that I saw a report on EE Times that the process has 8 layers of 52nm minim pitch metal, it actually has 5 layers of minimum pitch metal.
  • Intel has previously stated that the 14nm process wafer cost is 29% higher than the 22nm wafer cost. I have a really hard time reconciling that number with all the added masks at 14nm. First there are 8 mask layers required for the additional 4 metal layers, then 2 mask layers for the 2 air gap layers and likely 1 mask layer for the under fin doping. Then there are 1 additional cut mask for fins (2 versus 1 for 22nm), 1 cut mask each at contact and M0 and 10 cut masks for metals M1 through M5. In all I see an approximately 50% increase in both masks and process complexity.

    IBM
    The final paper I wanted to comment on from the session is the IBM paper on their 14nm technology. Where Intel and TSMC produce FinFETs on bulk wafers IBM produces FinFETs on SOI. The use of SOI enables IBM to integrate eDRAM on the same wafer with only 2 masks (my estimate). eDRAM is much more area efficient for cache than SRAM and with the huge cache sizes required for processors and SOCs eDRAM can save a lot of die area. I believe the IBM eDRAM process only requires 1 mask to form the trench DRAM capacitor and 1 additional mask for a thick gate oxide for the access transistors. The IBM process definitely leads in the complexity category with 15 metal layers and the eDRAM. This process is likely targeted at IBMs internal processors used for high end servers where processor cost is really not much of a consideration. The process pitches are 42nm for fin, 80nm for gate and 64nm for metal. IBM gave the most process details of the three papers with a block level process flow, always a favorite of mine. This is a very impressive high performance process.

    Comparison and conclusions
    The following table compares the density for the three processes.

    [TABLE] align=”center” border=”1″
    |-
    | style=”width: 133px” |
    | style=”width: 120px; text-align: center” | IBM
    | style=”width: 114px; text-align: center” | Intel
    | style=”width: 108px; text-align: center” | TSMC
    |-
    | style=”width: 133px” | Gate (CPP)
    | style=”width: 120px; text-align: center” | 80nm
    | style=”width: 114px; text-align: center” | 70nm
    | style=”width: 108px; text-align: center” | 90nm
    |-
    | style=”width: 133px” | Metal
    | style=”width: 120px; text-align: center” | 64nm
    | style=”width: 114px; text-align: center” | 52nm
    | style=”width: 108px; text-align: center” | 64nm
    |-
    | style=”width: 133px” | Gate x Metal
    | style=”width: 120px; text-align: center” | 5,120nm2
    | style=”width: 114px; text-align: center” | 3,640nm2
    | style=”width: 108px; text-align: center” | 5,760nm2
    |-

    A few final observations from this session:
    [LIST=1]

  • To my mind Moore’s law is alive and well not only technologically but I also believe these processes deliver cost per transistor reductions as well. For some of the foundry processes cost reduction is modest at 16nm/14nm because they maintained the same BEOL as previous generations but moving forward to 10nm I expect to see significant cost reductions with a return to full scaling.
  • Intel has the densest process when measured by the gate x metal pitch metric. What isn’t clear is how an Intel die size would compare to an IBM die size for a die with a large cache. Intel’s SRAM is 0.0588um2 whereas IBM’s eDRAM cell is 0.0174um2 providing a significant potential area saving for cache.