TSMC – Page 34 – SemiWiki

September 1, 2015August 22, 2024

TSMC is the Top Dog in Pure-Play Foundry Business

TSMC is the Top Dog in Pure-Play Foundry Business
by Pawan Fangaria on 09-01-2015 at 12:00 pm
Categories: Foundries, GlobalFoundries, TSMC

We all have echoed the fact that the arrival of fabless business model in the semiconductor industry has transformed it completely. The book, “Fabless: The Transformation of the Semiconductor Industry” provides several stories around that. In the backdrop of that, one key point to ponder upon is the start of pure-play foundries; TSMC being the initiator in 1987. The availability of pure-play foundries gave the boost and courage to small as well as large players around the world to start designs without owning fabs. The net result was a flood of fabless design companies and innovations in designs around the world. This is not without the pure-play foundries innovating themselves too. TSMC and subsequent foundries provided leading edge processes and technologies in manufacturing. Today, pure-play foundries provide manufacturing services not only to fabless companies but also to IDMs. Hence, looking at the other side of the coin, it would not be imprecise to say that the pure-play foundry model also transformed the semiconductor industry.

After TSMC, about ten more pure-play foundries were founded around the world, the latest being GLOBALFOUNDRIESin 2009. According to the first quarter sales figures of 2015, three pure-play foundries (TSMC, GLOBALFOUNDRIES, and UMC) occupy the ranks within top20 semiconductor companies in the world, TSMC being 3[SUP]rd[/SUP]. Interesting to note among the pure-play foundries is the following –

The percentage share of these top3 pure-play foundries clubbed together in the overall pure-play foundry sales is 79% and above; $33.68 B out of a total of $42.4 B in 2014, and $9.32 B out of a total of $11.4 B in 1Q 2015, i.e. 82%.

If we do a further analysis of TSMC’s share among the top20 pure-play foundries (i.e. the three foundries as stated above), it’s 74% in 2014 ($24.976 B out of $33.68 B) and 75% in 1Q 2015 ($6.995 B out of $9.318 B). What do we call TSMC in such a scenario?

Let’s also see the pure-play foundry business in recent perspective where we know TSMC had lost some business due to Samsungstarting in-house manufacturing of its Exynos and Appleallocating a part of their processors to Intel and Samsung. However, Apple is expected to come back to TSMC’s 16nm FinFET for their A9 processors in iPhone7. There are reasons for it; I’m not going in those details here. However, I would like to debate on how TSMC influences the overall pure-play foundry business. Let’s look at the following chart reported by IC Insights –

This chart depicts the usual trend of the best growth for pure-play foundries in Q2 every year (double-digit growth compared to Q1), i.e. ahead of Q3, the best quarter for total IC industry. However, in 2015 that trend was broken; in Q2 the sales declined slightly compared to Q1 instead of increasing as was seen in previous years. The reason – 5% decline in TSMC’s revenue in Q2 compared to Q1. If TSMC’s 5% change in revenue can change the pure-play industry trend, then that’s definitely the ‘Top Dog’ in the industry. Although there are competing technologies possessed by other foundries as well, I would go back to my hypothesis that business leadership along with technology leadership is the key to establish someone as the ‘Top Dog’.

For TSMC, rest of this year and 2016 are certainly looking better. IC Insights forecasts the overall pure-play foundry sales in Q4 2015 to reach over $12 B, the highest ever. The IC Insights pure-play foundry report is HERE for your reference.

Also read:
Changing Trends at the Top of Semicon Space. The chart in this article provides the sales numbers of the top3 pure-play foundries mentioned above.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

August 20, 2015

Older Nodes Get New Life With Ultra Low Power Variants for IoT

Older Nodes Get New Life With Ultra Low Power Variants for IoT
by Tom Simon on 08-20-2015 at 12:00 pm
Categories: EDA, General, IoT, Mobile, TSMC

Ever since I can remember, and I’ve been in EDA since the early 80’s, new process development has largely focused on the latest nodes. Trailing nodes were quickly put into support mode. New nodes benefited the most from static and dynamic voltage reduction efforts, as well as improvements in flows and performance. Only a small number of niche processes, usually produced by smaller captive fabs, were tuned over time for improvements. But the IoT has changed this.

With projected volumes for IoT chips in the billions, foundries, EDA and IP vendors have put a new emphasis on revisiting their offering for larger nodes. The biggest motivation for this is the need for lower power and the proliferation of wireless. When we say lower power, it’s not about needing fewer cooling fans, its about running for months on solar power, or making a wearable last for weeks before it needs to be recharged.

For wearables, using a larger battery is not an option. A typical wearable LiPo battery might have less than 20 milliamp-hours at 3.7V. Sleep modes need to be in the uA, not milliamp range. Every trick in the book is needed: voltage Islands, power islands, low leakage libraries, sub threshold operating voltages.

Apparently TSMC has been thinking about these issues for a while and concluded that updating processes alone will not solve the power problems faced by new products. So TSMC has announced the development of IoT platforms with several of their OIP partners. For its part TSMC is rolling out ultra low power (ULP) versions of its 0.18u, 90nm, 55nm, 40nm and 28nm processes. Several of them will come with embedded flash and the ability to support radio design.

TSMC expects the ULP processes to reduce operating voltages by 20% to 30%. That combined with standby power reductions promises to offer 2X to 10X increases in battery life.

TSMC has announced that the following partners are participating:

ARM – IoT subsystems for the Cortex-M and Cordio radio IP. Running on the 55nm ULP process, they can run below one-volt, saving significant power.

Cadence – Also targeting 55nm ULP, they offer Tensilica Fusion DSP’s for sensor and peripheral interfaces operating at optimal power levels. Tensilica cores are available for WiFi/IoT connectivity for wearables and other IoT applications. 40ULP and 28ULP are also available.

Dolphin Integration – Bringing ultra low power methodologies and flows for designing ultra low power designs that include voltage and power islands. They are providing tools to effectively reduce dynamic and static power for designs targeted by the TSMC partnership.

Imagination – IP for ultra low power designs. They are providing processor cores, wireless and other ancillary functions implemented as reference IoT subsystems. Imagination offers comprehensive IP for building a large number of IoT applications.

Synopsys – Working on an integrated IoT platform on TSMC’s 40nm ULP process. This will include a broad range of DesignWare IP. The highlights are the ultra low power ARC EM5D processor core, power and area optimized libraries, memory compilers, NVM as well as a number of IO and sensing blocks.

All of this represents a large commitment on the part of TSMC and their partners to create the processes and flow enablers necessary to fulfill projected design and volume demands fron the explosive growth of ultra low power connected designs for the IoT.

For more information on applications for different process nodes look on their site.

August 7, 2015

Is 7nm Coming to the TSMC OIP Ecosystem Forum?

Is 7nm Coming to the TSMC OIP Ecosystem Forum?
by Daniel Nenni on 08-07-2015 at 4:00 pm
Categories: FinFET, Foundries, TSMC

This is the 5[SUP]th[/SUP] TSMC Open Innovation Platform Ecosystem Forum and it is not to be missed. Please note that the location has moved from the San Jose Convention Center to the Santa Clara Convention Center which is literally right across the street from the new Levi’s Stadium. If you haven’t been to the new stadium you really should take a tour and stop by the SF 49ers Museum. Public tours run between 10am and 6pm and yes they have WiFi.

The new location will increase attendance significantly this year (my opinion) so you had better register now because space is limited. In addition to networking with 1,000+ semiconductor professionals you will get to hear from TSMC’s executives on what is new and improved for the different processes and surrounding ecosystem: 28nm, 16nm, 10nm, and I would bet 7nm will also be mentioned if not formally announced.

You may also get to hear from one of TSMC’s leading customers. At the TSMC Technology Symposium last April the guest speaker was Avago CEO Hock Tan. Since then Hock has engineered the acquisition of Broadcom for $37B. Previously he acquired LSI Logic for $6.6B so I would definitely like to hear a semiconductor industry update from an executive of his caliber, absolutely.

The event starts at 9am on Thursday, September 17[SUP]th[/SUP]. After the ninety minute executive presentations there are 30 technical papers divided into three tracks for EDA, IP, and Services. The paper abstracts are now up on the OIP website. And of course there will be a vendor expo with 80 vendors bearing gifts and the latest news on design enablement. Rumor has it Solido Design will be giving away the elite SemiWiki.com stylus penlights so you may want to go there first.

Click HEREfor the event overview, agenda and registration

|-
| 11:30 – 12:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Exploring Custom Metal Stacks for Advanced Node IC Design Using Early StarRC Extraction
|-
| align=”center” valign=”top” | Synopsys
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Migrating ARM Cortex-A53 designs From 28HPM to 28HPC+ – Getting Two Designs Out of a Single Implementation
|-
| align=”center” valign=”top” | ARM
|-

|-
| 12:00 – 13:00
| colspan=”3″ align=”center” valign=”top” | Lunch
|-
| 13:00 – 13:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Thermal and Color-aware Reliability Verification for Sub-16nm FinFET Designs
|-
| align=”center” valign=”top” | Ansys Inc.
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | High-Speed SerDes Design in Advanced TSMC Process: Architecture Implementation
|-
| align=”center” valign=”top” | GUC
|-

|-
| 13:30 – 14:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Custom Device Array- Place, Route, Simulate Prior to Layout
|-
| align=”center” valign=”top” | Cadence
|-

|-
| 14:00 – 14:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Hierarchical Fill Methodology for Advanced Nodes
|-
| align=”center” valign=”top” | Mentor Graphics
|-

|-
| 14:30 – 15:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | IC Packaging centric approach to design fanout-out WLCSP (InFO) designs
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Rapid Implementation of IoT end-point sensor devices using ARM and TSMC IP
|-
| align=”center” valign=”top” | ARM
|-

|-
| 15:00 – 15:30
| colspan=”3″ align=”center” | Coffee Break
|-
| 15:30 – 16:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | 2-5X productivity improvement in converging to a DRC-clean cell design—Qualcomm’s experience with Calibre RealTime
|-
| align=”center” valign=”top” | Mentor Graphics
|-

|-
| 16:00 – 16:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Synopsys’ PrimeTime POCV Improve Productivity and PPA in FinFET Designs – NVIDIA Experience

|-
| align=”center” valign=”top” | Synopsys
|-

|-
| 16:30 – 17:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | TSMC Advanced Node EMIR analysis
|-
| align=”center” valign=”top” | Cadence
|-

|-
| 17:00 – 17:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | IC Compiler II key in accelerating time-to-market for HiSilicon’s next-generation 10-nm advanced SoC’s
|-
| align=”center” valign=”top” | Synopsys
|-

|-
| 17:30– 18:30
| colspan=”3″ align=”center” | Social Hour
|-

The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share real case solutions to today’s design challenges. Success stories that illustrate best practices in TSMC’s design ecosystem will highlight the event.

More than 90% of last year’s attendees said that “the forum helped them better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies to address your design challenges!

This year, the forum is a day-long conference kicking-off withtrend-setting addresses and announcements from TSMC and premier IC design company executives.

The technical sessions are dedicated to 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies, and an Ecosystem Pavilion feature up to 80 member companies showcasing their products and services.

Click HERE for the event overview, agenda and registration

July 18, 2015

TSMC (Apple) Update Q2 2015!

TSMC (Apple) Update Q2 2015!
by Daniel Nenni on 07-18-2015 at 8:00 pm
Categories: Foundries, TSMC

The TSMC quarterly conference call was last week and of course it stirred up quite a bit of controversy. Let me share with you my experience, observations, and opinions and maybe together we can come up with an accurate prediction for 2016. First let’s take a look at 20nm and what people now call the “Apple effect.”

Correct me if I’m wrong here but this is how I remember it: The TSMC 20nm process was highly criticized for cost, power leakage, and yield prior to the arrival of the Apple A8 and A8x SoCs. As we now know 20nm was the fastest ramping process in the history of TSMC and the A8 powered iPhone 6 is a huge success. This much is now well documented.

Next came TSMC 16nm. Unfortunately, the first 16nm process did not meet expectations of the fabless semiconductor ecosystem as compared to Intel and Samsung 14nm. Intel 14nm was faster and denser and Samsung 14nm was lower power. This was clearly a missstep for TSMC but they learned from it and came back with 16FF+ (second generation FinFETs) which is now the best performing process of its kind. TSMC openly makes this claim but I have confirmed it with several early access IP and fabless companies and they would know. 16FF+ based mobile products will hit the market in Q4 2015 and you will be impressed, absolutely.

TSMC 16FF+ does use the same BEOL (back end of line) as 20nm, which is the second half of the chip manufacturing process. The FEOL (front end of line) however is quite different. In fact, you will see a difference between the original TSMC 16nm and 16FF+ which has resulted in a significant PPA improvement (performance, power, and area). So when Morris Chang claims that 16FF+, which is technically their second generation FinFET, will be an even faster ramp than 20nm I believe it to be true.

As I predicted last year, Apple chose Samsung 14nm LPE for the iPhone6S (A9 SoC) and TSMC 16nmFF+ for the iPads (A9x). I stand by that prediction even though on the conference call Morris Chang said that in 2016 TSMC 16nm market share will be much greater than “our next competitors.” Given that Apple and QCOMM, TSMC’s two largest customers, are currently using Samsung 14nm there is really only one way this prediction can come true: Apple and QCOM will use 16FFC (TSMC’s third FinFET generation) for their SoCs in 2016.

TSMC also mentioned that 10nm will be in production in Q1 2017 which supports the above prediction that the iProducts released in 2016 will not be 10nm. The other interesting thing to note is the PPA numbers for 10nm: 15% speed gain at the same total power, or more than 35% power reduction at the same speed, and with k density of 2.2 times that of 16nm FinFET. I can tell you that Apple will not accept a 15% speed gain for a new process. I was told that the new 16FFC process due out mid 2016 was built “with” Apple so I would expect the same for 10nm. 16nm FF+ provides a 40% higher speed and 60% power savings over 20nm. My prediction is that the Apple version of 10nm for the 2017 iProducts will offer a minimum 25% speed increase.

Sound reasonable?

The conference call transcript is HERE.

July 11, 2015August 22, 2024

Who Needs to Lead at the 14, 10 and 7nm nodes

Who Needs to Lead at the 14, 10 and 7nm nodes
by Scotten Jones on 07-11-2015 at 12:00 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, Samsung Foundry, TSMC

IBM recently disclosed a working 7nm test chip generating a lot of excitement in the semiconductor industry and also in the mainstream media. In this article I wanted to explore the 14nm, 10nm and 7nm nodes, the status of the key competitors at each node and what it may mean for the companies.

Continue reading “Who Needs to Lead at the 14, 10 and 7nm nodes”

July 9, 2015

After Five Years, 28nm Future Remains Bright!

After Five Years, 28nm Future Remains Bright!
by Daniel Nenni on 07-09-2015 at 2:00 pm
Categories: Foundries, TSMC

Five years ago TSMC started 28nm mass production and it went on to become one of the most versatile and successful process technologies in history. The first wave was triggered by an unprecedented demand for application processors from smartphone and tablet vendors. Today it’s widely assumed that 28nm demand will continue growing with the introduction of mid- and low-end smartphones, burgeoning Internet of Things applications, and other second-wave opportunities such as automotive.

Not resting on its laurels, TSMC recently announced several significant process improvements to offer its customers and they are increasing capacity to accommodate strong ongoing demand for 28nm solutions.

As we all know, the performance requirement is different for entry level, mainstream, and high-end products. However, today’s performance spec for high-end products will become tomorrow’s mid-range spec so TSMC needs to continue to improve its portfolio by offering a range of options. Accordingly, the company introduced 28HPC to address 64-bit CPU core conversion to roughly 2GHz performance because 64-bit CPU performance is limited by the power budget.

This year they added 28HPC+ that offers 15% faster speed compared to 28HPC. 28HPC+ can allocate more power budget to push CPU/GPC performance significantly over 2 GHz while staying within the same power budget. 28HPC+ also achieves an additional 30% performance at sign-off condition which allows designers to replace the 28HPC LVT transistors with 28HPC+ SVT transistors. As a result, it can reduce leakage by 80% on high-speed sensitive circuits. Equally impressive, TSMC has worked with its design ecosystem partners to support an easy IP migration from 28HPC to 28HPC+. As you can see from the blue box, all that’s needed is to re-characterize the standard cell library and SRAM complier. There is no change of I/Os. And you simply need to re-simulate and fine-tune analog devices in order to enjoy the greater values of 28HPC+.
The next innovation is 28ULP (ultra-low power). It is based on 28HPC with 30% power reduction and optimized for IoT and wearables. It provides a simple power grid, multiple gate length advantages, smaller die size, a broader portfolio of multi-source IPs, and a shorter cycle time that translates to a faster time-to-market. According to TSMC, when compared to FD-SOI, 28ULP is much more competitive in both performance and low-power. 28ULP offers multiple Vt options with multiple gate bias options, versus FD-SOI’s 2 Vt’s with body bias and gate bias at nominal Vdd.

It should be noted that the extensive body bias implementation in 28FD-SOI not only significantly increases design complexity but also die area.

RF is another trend addressed by 28HPC-RF and the proliferation of RF into LTE RF Transceiver and WiFi/BT combo applications. Advanced RF CMOS technology is needed for longer range and higher data rate, especially in mobile communication which is 4G/LTE now. And further demonstrating 28nm adaptability, TSMC is the first foundry to certify these technologies for automotive production. Multiple customers have completed automotive qualifications compliant with AEC-Q100 for grade-one specs.

Given its outstanding track record over the past five years, there is little doubt that the future for TSMC 28nm technology will continue to be very bright and highly productive, absolutely.

June 30, 2015

Why Did Intel Pay $15B For Altera?

Why Did Intel Pay $15B For Altera?
by Paul McLellan on 06-30-2015 at 12:00 pm
Categories: Foundries, FPGA, Intel Foundry, TSMC, Xilinx

While I was at the imec Technology Forum someone asked me “Why did Intel pay $15B for Altera?” (the actual reported number is $16.7B).

The received wisdom is that Intel decided that it needs FPGA technology to remain competitive in the datacenter. There is a belief among some people that without FPGA acceleration available for vision processing, search and other algorithms that map better onto a hardware fabric than a processor, then Intel will gradually have more and more competitors in the datacenter. Even if you only put that possibility at 50-50 (say) then the “only the paranoid survive” attitude is to get an FPGA acceleration solution anyway. Of course they don’t need to buy Altera to do that. I’m sure Altera (or Xilinx even) would be happy to sell them all the chips they need. But at some point that technology may need to be embedded in which case having it on the same process already counts for something.

The next question was “Couldn’t they just build an FPGA solution themselves? It wouldn’t cost $15B.” At the technical level I am sure that the answer is that they could do it. Intel has great engineers and if they put their mind to it I’m sure they could produce something.

But I see 3 problems with doing it in-house.

[LIST=1]

Time. Intel might be able to design a suitable fabric but how many years would it take them to get it up to a competitive standard. Altera and Xilinx have spent decades doing it. Intel would be trying to catch them from a standing start.

Patents. It is basically impossible to design an FPGA without violating Altera and Xilinx’s patents. Those two companies have a cold war of mutually assured destruction. But anyone else would get problems if and when they got commercial traction. Intel would probably get problems even earlier. If (say) Xilinx felt Intel was violating their patents blatantly they may launch. Against an FGPA startup, the most they could win would be their entire cash balance which probably wouldn’t cover the legal fees.

Software. FPGA is as much about software as hardware. I once did due-diligence for a VC on a hardware fabric (arrays of tiny CPUs) and told the VC to run away fast because the company didn’t even realize they were basically in a software business, where they had no expertise. They, and Intel, could probably build the hardware fabric. But could they build and mature a software tool chain allowing them to take C and other software languages and move them into the fabric seamlessly? That takes years too.

Besides, Intel has already tried to grow their own FPGAs from seed with Tabula and Achronix, in both of which they were major investors and provided foundry services. Tabula closed its doors. Achronix’s are still open but rumors are not enthusiastic.

So if Intel wants a mature FPGA fabric with a working tool chain that allows compilation of offload software into hardware, they pretty much have to buy Altera or Xilinx. I don’t think Lattice have powerful enough software or large enough arrays, it’s not what they do. Xilinx are deep partners with TSMC, 10nm just announced. Altera are partners with…Intel (and TSMC too, to be fair). So easy decision which girl to chase at the dance.

The next question. “So why would Intel want to run a merchant FPGA business?” I have to say that I agree with the question. If I put myself in Intel’s shoes I wouldn’t want to. Mostly they are shipping TSMC silicon and have no opportunity to move it into an Intel fab. The Intel/Altera 14nm arrays are not even sampling (or even taped out, I hear). For anti-trust reasons they may have had to promise to keep the business going as a condition of the deal closing, but otherwise the first thing I would do is shut it down, or at least not invest in it for the future. It doesn’t need enough wafers to “fill the fab”. And it doesn’t move the needle in revenue either (Altera is a little less than $2B, all TSMC silicon, and Intel is $60B or so). So Altera’s merchant business is a pure distraction from Intel’s business in the datacenter and notebooks.

Who benefits? Everyone else. The Altera 14nm FPGAs have ARM processors on them. Who in their right mind is going to kick off an ARM-based project on Altera FPGAs now? Xilinx would seem a much safer choice. They are not about to exit the merchant FPGA business, nor switch ARM out for Atom, nor fail to get timely access to ARM’s latest and greatest next-generation cores, or whatever your nightmare of choice is.

With regards to the acceleration in the datacenter question, there are two outcomes. One, it turns out to be really important, which bodes really well for Intel/Altera but also for the ARM/Xilinx ecosystem, which will be basically everyone else other than Intel, including some powerful players such as Qualcomm. Or, two, it isn’t a major factor. ARM’s partners can still compete on the basis of power, price and physical size and may get some traction. And Intel wasted $15B.

Also Read: Xilinx in an ARM-fueled post-Altera world

June 8, 2015

TSMC Shows 10nm Wafer!

TSMC Shows 10nm Wafer!
by Daniel Nenni on 06-08-2015 at 4:00 pm
Categories: FinFET, Foundries, TSMC

If you really want to know why I write about TSMC it is all about ego, my massive ego, absolutely. Blogs about TSMC and the foundries have always driven the most traffic and they most likely always will. Semiconductor IP is second, Semiconductor Design is third, and I don’t think that is going to change anytime soon:

SemiWiki BI: Daniel Nenni: TSMC: All
Total Blogs: 137
Total Views: 878600
Average: 6413

SemiWiki BI: Semiconductor IP: All
Total Blogs: 431
Total Views: 1641911
Average: 3810

SemiWiki BI: Semiconductor Design: All
Total Blogs: 1367
Total Views: 4157039
Average: 3041

TSMC came to the Design Automation Conference 16 years ago ushering in a new level of collaboration amongst the fabless semiconductor ecosystem. Other foundries have followed and one could argue that they are the center of the DAC universe. In that time TSMC has completed 15 reference flows (the latest being 10nm) with 7,500+ tech files, 200+ PDKS, and more than 8,600 silicon proven IP titles from .35u to 10nm.

Today, the first day of #52DAC, my prediction of a big crowd has come true. This year the big foundry buzz is around 10nm. TSMC is showing a 10nm wafer for the first time and everybody is wondering if in fact 10nm will arrive in 2016 like promised. I certainly believe it will and so does the majority of the fabless semiconductor ecosystem.

Let’s take a quick look at the TSMC process node revenue start history just for fun:

[LIST=1]

.35u 1996

.25u 1998

.18u 2000

.13u 2002

90nm 2005

65nm 2007

40nm 2009

28nm 2011

20nm 2014

16nm 2015

10nm 2016

7nm 2017

Seriously, we are doing four new process nodes in four years? The fabless semiconductor ecosystem is truly an amazing thing. In regards to process ramp challenges, I remember .13u being very difficult because of the new copper interconnect. 40nm was certainly not easy. 40nm was the last node where TSMC gave you the option of using recommended (yield centric) design rules. Which one of these nodes was the most challenging? You tell me. If you have a design horror story please share it in the comments section and I will give you a free Kindle version of “Fabless: The Transformation of the Semiconductor Industry“.

TSMC has the Open Innovation Platform Theater again this year in booth #1933. You can see the schedule HERE.The other TSMC related #52DAC activities are HERE:

TSMC’s booth is jam packed, probably because they are giving away iWatches and other cool stuff. TSMC also had some interesting IoT press today, one even mentioning 10nm:

Imagination and TSMC collaborate on advanced IoT IP platforms
Imagination Technologies (IMG.L) and TSMC announce a collaboration to develop a series of advanced IP subsystems for the Internet of Things (IoT) to accelerate time to market and simplify the design process for mutual customers. These IP platforms, complemented by highly optimized reference design flows, bring together the breadth of Imagination’s IP with TSMC’s advanced process technologies from 55nm down to 10nm…

Cadence Announces Collaboration with TSMC on IoT IP Subsystem
Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced that it is collaborating with TSMC on the development of an Internet of Things (IoT) intellectual property (IP) subsystem demonstration platform for TSMC’s ultra-low power (ULP) process. Targeting wearable, home automation, always-on and industrial control applications, this IP subsystem, with the support of the Cadence suite of digital and custom/analog tools, provides the opportunity to simplify IoT designs and accelerate the time to market for mutual customers…

Synopsys and TSMC Collaborate to Develop Integrated IoT Platform for TSMC 40-nm Ultra-Low-Power Process
Synopsys, Inc. (Nasdaq:SNPS) today announced a collaboration with TSMC to develop an integrated Internet of Things (IoT) platform on TSMC’s 40-nm ultra-low-power (ULP) process technology. The IoT platform incorporates a broad range of DesignWare® IP, including an integrated sensor and control IP subsystem with the ultra-low-power ARC® EM5D processor core, power-and area-optimized logic libraries, memory compilers, NVM, MIPI and USB interfaces as well as an analog-to-digital converter (ADC). The high-performance, low-power IoT platform provides designers with a pre-validated solution that enables them to deliver the energy-efficient, always-on processing required for applications such as sensor fusion and voice recognition…

May 29, 2015September 1, 2024

"Cook’s Law" supersedes "Moore’s Law"-its impact on Apple, Samsung, TSMC & Intel

"Cook’s Law" supersedes "Moore’s Law"-its impact on Apple, Samsung, TSMC & Intel
by Robert Maire on 05-29-2015 at 7:00 am
Categories: Foundries, Intel Foundry, Samsung Foundry, TSMC

Apple drives the semi industry harder than Wintel ever did: Is winning Apple’s chip business a pyrrhic victory? Is 14nm done before it starts? Too short to be profitable?

Chips marching to an Apple cadence…
In the “old days” when Wintel ruled the roost and drove the semi industry, it was driving spending cycles based on new versions of Windows that stimulated unit volume of PCs and thus chips.

New versions of Windows did not specifically demand nor require new technology nodes of Intel processors which were released at the standard “Moore’s Law ” cadence. Windows releases and Intel technology nodes were not interdependent and were relatively loosely linked. It was a “nice to have” if new processors came out at the same time as a new version of Windows but it wasn’t a “must have”

In today’s world, a new version of the iPhone can’t be released unless a new processor is inside to drive it to new heights. The product, processor and software are inextricably linked.

Given that Apple is driving the train with its fall, seasonal roll out of the new iPhone every year, everybody else, who supplies Apple (this means semi suppliers) has to be on board or be left behind at the station. In essence this means that Apple is setting the schedule for the next semiconductor technology node roll out, not the semiconductor industry itself or Moore’s Law as it had previously been.

Apple is forcing and imposing a schedule upon its suppliers, which may be different than a “natural” cadence and likely negatively impacts those who are forced to follow.

Is 14nm done before it even starts?
We are amazed by the level of BS in the industry that competing players are throwing around about 14nm and now 10nm. Both Samsung and TSMC are pushing their competing press releases about 10nm in 2016 before the ink is even on the paper for 14nm orders.

Going by whats in the trade rags and around the industry, we have moved on so quickly from the issues of 14nm and FinFET on to who has the lead at 10nm it makes my head spin. Apple won’t have a product out until the fall and we have already started to talk about who will win the A10 for 2016.

If we believe the hype (and I’m not sure wether we do or not…) it sounds like 14nm will be another “lite” node much like 22/20nm was. The last “good” node being 28nm. However there are those in the industry that say that 10nm will be another “good” node much like 28nm.

It feels like 14nm is already “old news” and the PR wars and jockeying for position at 10nm is even more severe than it was at 14nm….and who does this all benefit??….Apple.

Is Apple chip business a “loss leader”?
When you take into account the massive effort to ramp, the less than ideal yields and the competitive positioning needed to win Apple’s business its not likely very profitable at the end of the day.

One of the main reason’s we would suggest this is that the cost of manufacturing semiconductors is primarily the amortization of the manufacturing costs over as many years and products as is possible. If Apple forces chip makers to move on before they get a chance to amortize the cost of equipment and R&D needed to get to that technology node then how do you make money? Certainly not on Apple. The only way you can make money is by trying to amortize that cost on the backs of trailing technology companies and no one wants to pay up for what is perceived as trailing edge devices.

We think that Apple has made it a more dangerous, potentially much less profitable game by both compressing the technology nodes and forcing them to their own cadence.

Cook’s Law..
“Supplier competition goes up exponentially with each new supplier or technology node added”

The semiconductor industry may be just as much a slave to Apple’s whims as are the Apple slaves at the Foxconn factories in China. Walmart may have a million employees in the US but Apple has more if you count suppliers globally.

If you are going to be a slave at least be a high priced slave. We have a hard time seeing the semiconductor industry getting better profitability out of Apple given the current competitive supplier dynamics involved.

We don’t see this changing soon as neither TSMC nor Samsung are likely to drop out of the race. Maybe Apple kicks Samsung to the curb again just to remind them of their place as a supplier but they will keep coming back. Maybe Global Foundries has the right idea as they are currently working on Qualcomm 14nm parts and not Apple A9. Maybe they figured out it was a bad game to play or maybe they were just too late. Apple has been the maestro of playing its suppliers and they continue to write the rules and set the standards

Can equipment companies win?
One would think with technology nodes coming fast and furious that equipment companies would be rolling in orders but that is obviously not the case. So where is the disconnect? Business is good but not great on the foundry side of life. Could it be that chip companies recognize that we have “lite” technology nodes, that are relatively short lived and are spending accordingly to not invest too much money in a node thats over as soon as it starts. Could it also be that the equipment for older nodes can get rolled over into new nodes and “reused” more quickly as not as much capacity is needed at trailer nodes as used to be the case in the past?

Even given these two factors its still going to be hard to not spend incremental money when you start talking about quadruple patterning at 10nm and below. Lots of etch and dep tools, lots of stuff to go wrong needing yield management. EUV is nowhere to be seen at 10nm and 7nm may be “iffy”.

Likely positive WFE spend trends at 10nm…
If 10nm turns out to be more than the “lite” 22/20nm node or what seems like a “lite” 14nm node that would obviously be good for the likes of Lam, AMAT & KLAC. Less so for ASML.

As far as the stocks go, we remain positive on Lam and KLAC, feel that AMAT is fully valued and ASML is overvalued…..based on these longer term trends. These should be interesting topics at the upcoming SemiCon West show……

Robert Maire
Semiconductor Advisors LLC

Also Read: Why does Apple do business with Samsung?

May 26, 2015September 1, 2024

Why does Apple do business with Samsung?

Why does Apple do business with Samsung?
by Daniel Nenni on 05-26-2015 at 10:00 pm
Categories: Foundries, Intel Foundry, Mobile, Samsung Foundry, TSMC

The Apple and Samsung relationship is an interesting one. On one hand they have co-developed some of the most innovative products on the market today (iPod, iPhone, iPad, iWatch) yet they are fierce competitors in the mobile market. Some call this type of business relationship “frenemies” others refer to the old Italian proverb “keep your friends close, but your enemies closer.” Personally I refer to it as “foundry business as usual.” Let’s take another look at the Apple/Samsung relationship and see if we can get a better picture of what is really going on here. This of course is based on my experience, observations, and opinions so feel free to correct me if I’m wrong, but I’m not.

Apple became a chip company in the early 1990s with the assistance of VLSI Technology. This was using the ASIC business model where Apple could “toss” an RTL level design over to VLSI and have them deliver finished chips. The first chip was for Apple’s PDA, the Newton, which lost out to the much easier to use BlackBerry and Palm Pilot.

The smartphone (iPhone) was the next device to usher in semiconductor design at Apple. In 2007 the first iPhone was powered by the APL0098 SoC designed by Apple and the newly created Samsung Foundry Division using the same ASIC business model that VLSI Technology pioneered. The first chip used Samsung’s 90nm technology which was one process behind TSMC’s 65nm that offered twice the gate density and a power reduction of up to 50 percent.

The next two iterations of the Apple SoC were released in 2008 and 2009 using Samsung’s 65nm technology. At the same time TSMC was delivering 40nm chips with twice the density of 65nm with significantly reduced power requirements. In 2009, 2010, and 2011 Apple used Samsung’s 45nm which delivered density and power requirements just below TSMC’s 40nm. In 2012 and 2013 Apple used Samsung’s 32nm process but TSMC was already at 28nm which again offered increased density and lower power. At the end of 2013 (iPhone 5+ and iPad Air) Apple used Samsung’s 28nm. Apple also ushered in the 64-bit smartphone with the iPhone 5s beating industry SoC leader Qualcomm.

For the iPhone6 and iPad Air2 in 2014, Apple switched to TSMC’s 20nm which offered a 1.9x density and 25% power advantage over 28nm. The switch from Samsung Foundry to TSMC is a hotly debated topic especially since Apple is now back at Samsung for the 14nm A9 to be released in September of 2015. According to analyst estimates, Apple paid Samsung $2.7 billion for chips in 2014 which is significantly lower than the $4.3 billion Apple paid Samsung in 2013. So yes, the Apple business is a very big deal for the foundries, absolutely.

Apple claimed its semiconductor manufacturing independence with the 2008 acquisition of P.A. Semiconductor and the 2010 acquisition of Intrinsity which enabled them to move from the ASIC business model to the fabless semiconductor powerhouse they are today. If you want my opinion, which clearly you do if you are reading this, Apple bases the process technology decisions on technology and the ability to deliver said technology, simple as that.

I know that Apple evaluated TSMC’s 28nm for the A6 and A6x SoCs but since TSMC was the only foundry yielding at the time TSMC’s 28nm pricing and capacity were in question. At 20nm however, Apple wrote TSMC a very large check to get right-of-first-refusal and most-favored-nation pricing which squeezed out competing SoC vendors (QCOM, MEDIATEK).

At 14nm Samsung developed an LP process specifically for Apple which started risk production in Q4 of 2014 making it viable for the Apple A9 SoC (iPhone 6+) release in Q3 2015. The big shocker here is that Samsung released their own 14nm SoC (Exynos) for their flagship mobile device the Galaxy S6 in the first half of 2015 beating everyone’s 14nm delivery expectations, including my own.

TSMC was two quarters behind Samsung with their higher performance 16nm FinFET++ implementation which will be used in the lower volume Apple A9x SoC business for the iPad refresh in Q4 2015 (the A9 versus A9x volumes are reportedly 70% versus 30%). I also heard that Apple evaluated Intel Custom Foundry 14nm, but to no avail.

10nm will be the next foundry battleground. Samsung and TSMC have both discussed taping out 10nm customer designs in the fourth quarter of 2015 which fits the timeline for Apple’s next product refresh using the A10 and A10x SoCs. Intel on the other hand has been very quiet which is not necessarily a good sign for the competition. Intel surprised the industry with 22nm FinFETs. Another 10nm surprise could certainly be in the making. My guess is that Apple will go to TSMC for 10nm but at this point it is just a guess.

Bottom line: Today, Apple is clearly the most influential foundry customer worth billions of dollars in revenue annually. Apple’s regular product refresh is now driving the foundries harder than I have ever seen and that includes Intel and Samsung. Competition is what makes the fabless semiconductor ecosystem strong and who better than Apple to lead that effort?