TSMC – Page 34 – SemiWiki

September 27, 2015

How to Build an IoT Endpoint in Three Months

How to Build an IoT Endpoint in Three Months
by Tom Simon on 09-27-2015 at 7:00 am
Categories: Arm, Foundries, IP, TSMC

It is often said that things go in big cycles. One example of this is the design and manufacturing products. People long ago used to build their own things. Think of villagers or settlers hundreds of years ago, if they needed something they would craft it themselves. Then came the industrial revolution and two things happened. One is that if you wanted something like furniture or tools you were better off buying them. The other was there was a loss of skills; people ‘forgot’ how to make things. This meant that the ability to create was concentrated in the hands of a few, and individuals had less control over what was available to them.

The maker movement has changed all that. The ability to design and build things has come full circle. Now if you want to design with 3D Printers and Arduino boards you can design a range of things, from simple everyday items to sophisticated appliances. In many ways the Internet of Things was started through this same pathway. People took low cost development systems and tools, added sensors, wireless and often servos to make a wide variety of useful things.

Semiconductor design has followed an analogous path. Early on design teams were small and they built chips that became the components of that era’s products. I remember calling on chip design companies in the late 90’s where it was literally three guys with a Sun workstation running layout software.

That era has ended and it seems that recently the only feasible way to design chips was at places like Nvidia, Intel, Freescale, Marvell, etc. They can apply design teams with hundreds of people to build their products. If you had an idea for a design and did not have the manpower, your idea went un-built.

However, things are changing again. The same market and technology forces that drove the maker movement, and pushed for standardization of building blocks, has spilled over into the internals of chip design. With the need for increased sophistication, the tools for building integrated platforms for IoT have been growing and maturing. We all know the formula by now: MCU, on board NVM, one or more radios, ultra low power, security, interfaces to sensors and a SW development environment to build user applications.

Differentiation is the key to success; product developers know they need to optimize their platform for their specific needs. ARM recently embarked on a project to test out the real world feasibility of having a small team build a custom IoT end point device in a fleeting 3 months. ARM used the TSMC Open Innovation Platform Forum in September to present their results.

ARM Engineering Director Tim Whitfield gave a comprehensive presentation on their experience. The challenge was to go from RTL to GDS in 3 months with 3 engineers. additionally, there were hard analog RF blocks that needed to be integrated. They went with the ARM mbedOS to make it easy to prototype. They also included standard interfaces like SPI and I2C for easy integration of external sensors.

ARM used their arsenal of building blocks which includes the Cortex M3, Artisan physical IP, mbedOS, Cordio BT4.2, ancillary security hardware and some TSMC IP as well. The radio was the most interesting part of the talk. A lot of things have to be done right to put a radio on the same die as digital. The Cordio radio is partitioned into a hard macro containing all the MS and RF circuitry. In the hard IP there is also real-time embedded firmware and an integrated power management unit (PMU) – critical for effective low power operation. It comes with a Verilog loop-back model for verification. The soft IP for the radio is AMBA-3 32-bit AHB compliant. It is interrupt driven and can operate in master & slave mode with fully asynchronous transmit and receive.

When adding the radio to the design, designers are given guidelines to avoid supply coupling in the bond wires. This is provided by adding 100pF decoupling per supply. They used CMOS process friendly MOM caps. They did receive some guidance from the radio team on how to prevent substrate coupling. They used a substrate guard ring with well-ties. Tim suggested that the guard ring could possibly be delivered as a macro in the future.

They discovered that if there was no cache that 80% of their power would be used for reading the flash and 20% used running application code. So they reduced the power overhead by using caching. Tim sees opportunity to further improve power performance with additional cache enhancements.

They already taped out in August, and are now waiting for silicon from TSMC in October. That, of course, will be the real test. Whatever lessons learned will be applied to improve the process for customers down the road.

This is certainly just a “little bit more” impressive than a maker getting their Arduino project working. Nonetheless, it is definitely a branch of the same tree. Enabling this kind of integration and customization democratizes product development and will in turn create new opportunities. I look forward to hearing how the first silicon performs.

September 22, 2015

New Sensing Scheme for OTP Memories

New Sensing Scheme for OTP Memories
by Paul McLellan on 09-22-2015 at 7:00 am
Categories: IP, Kilopass Technology, TSMC

Last week at TSMC’s OIP symposium, Jen-Tai Hsu, Kilopass’s VP R&D, presented A New Solution to Sensing Scheme Issues Revealed.

He started with giving some statistics about Kilopass:

50+ employees
10X growth 2008 to 1015
over 80 patents (including more filed for this new sensing scheme)
179 customers, 400 sockets, 10B units shipped

Kilopass’s technology works in a standard process using antifuse, causing a breakdown of the gate-oxide. Since the mechanical damage is so small it is not detectable even by invasive techniques, unlike eFuse technologies where the breaks in the fuse material are clearly visible by inspection. Over the generations of process nodes they have reduced the power by a factor of 10 and reduced the read access time to 20ns. Since the technology scales with the process, the memory can scale as high as 4Mb. It also is low power and instant-on.

Kilopass has focused on 3 major markets:

security keys and encryption. This only requires Kb of memory. The end markets are set-top box, gaming, SSD, military
configuration and trimming of analog. This also requires Kb of memory. End markets are power management, high precision analog and MEMS sensors
microcode and boot code. This requires megabits to tens of megabits. Applications are microcontrollers, baseband and media processors, multi-RF, wireless LAN and more

The diagram above shows how the programming works. There are two transistors per cell. The top one remains a transistor for a 0 (gate isolated from the source/drain) but after programming a 1 the oxide is punched through and the gate has a high resistance short to the drain. Since the actual damage to the gate oxide might occur anywhere (close to the drain or far from it), the resulting resistance is variable.

The traditional way to read the data is as follows. The bitline (WLP) is pre-charged, then the appropriate wordline (WLR) is used for access and the bitline (BL) is sensed and compared against a reference in the sense amp. Depending on whether the “transistor” is a transistor or a resistor, the current will be higher than the reference bitline current or not. If it is higher then a 1 is sensed, lower and a zero. The challenge is to sense the data fast, since the longer the time taken, the clearer the value, but all users want a fast read time. See the diagram below.
Historically this has worked well. In older nodes, the variations are small relative to the drive strengths of the transistors. But increasingly it gets harder to tell the difference between a weak 1 cell and an noisy 0 cell, which risks misreading the value. As a result it can take a long time to sense “to be sure.” As we march down the treadmill of process nodes, like many other things, the variation is getting so large it is approaching the parameters of the device itself. A new approach is needed.
The new approach the Kilopass have pioneered adds a couple of steps. Once the word line is used for access, after a delay the bitline reference is shut off. The bit line is sensed and the data latched and then the sense amp is shut off. The new sense amp incorporates the timing circuitry. The whole scheme is more tolerant of process variation and should be suitable for migration all the way to below 10nm. This approach is more immune to ground noise and has greater discrimination between weak 1 and noisy 0. Finally, shutting off the sense amp at the end saves power.
It turns out that this scheme works particularly well with TSMC’s process since their I[SUB]ref[/SUB] spread is half that of other fabs. The new sensing scheme coupled with tighter cell means doubling the read speed.

September 20, 2015

Four Takeaways from the TSMC OIP 2015

Four Takeaways from the TSMC OIP 2015
by Tom Dillinger on 09-20-2015 at 2:30 am
Categories: Foundries, TSMC

Paul M. did an excellent job summarizing the technical information that TSMC presented at the recent Open Innovation Platform symposium. I’d like to also share an impression on four areas that struck me as key to TSMC’s strategy.

Continue reading “Four Takeaways from the TSMC OIP 2015”

September 17, 2015

TSMC OIP: What to Do With 20,000 Wafers Per Day

TSMC OIP: What to Do With 20,000 Wafers Per Day
by Paul McLellan on 09-17-2015 at 4:42 pm
Categories: Foundries, TSMC

Today it is TSMC’s OIP Ecosystem Innovation forum. This is an annual event but is also a semi-annual update on TSMC’s processes, investment, volume ramps and more. TSMC have changed the rules for the conference this year: they have published all the presentations by their partners/customers. Tom Quan of TSMC told me that they will also provide a subset of the presentations TSMC gave to open the day.

The semiconductor business is driven by several large markets, the biggest of which is mobile. Fun statistics of the day are that mobile grew 26% from 2014-15 to shipments of 1.9B units. Since there are 4.3B worldwide mobile users, this means that the annual replacement rate is close to 50%. Global mobile traffic is forecast to go up 10X in 5 years from 30EB/yr in 2014 to 292EB/yr in 2019 (EB is exabyte).

For the future, the three big markets other than mobile are Internet of Things (IoT), Automotive, and High-performance Computing (HPC).

Let’s start with IoT: the market has a forecast CAGR from 2013 to 2018 of 21%. But the market is ripe in that 99.4% of devices are notconnected, so by 2022 the average house is forecast to have 500 smart devices. Of course every time you blink the IoT forecast goes up by a billion units but for sure it is real.

The big opportunity in automotive in the medium term is driverless cars or, before that, advanced driver assist systems (ADAS). Google’s driverless cars have done over 2M miles (with 16 minor accidents, all the fault of the other vehicle). Delphi/Audi drove a vehicle across the US from SF to NY (that I wrote about during DAC). Tesla will have autopilot in all their cars. One interesting potential change that autonomous vehicles might bring is to ownership. If you could have a car on-demand whenever you wanted one, would you own your own vehicle at all. Your car plan in a decade might be like your cellphone plan today, with various options depending on usage.

HPC is required to provide the back-end for all those mobile devices, typically in large datacenter aka cloud computing. The need for low latency and location awareness means that the mobile device needs to be providing local intelligence, but then low latency connect to the datacenter will be required too. This means that there will be upgrade cycles to all the base stations, of which there are (literally) millions.

TSMC provides a wide range of processes for different types of silicon. The process nodes mentioned here are where TSMC is working on bringing the process up; volume production is one (or sometimes two) nodes behind.

R&D overall is up 19% year-on-year from 2014 to 2015. It was $1.9B in 2014 and will be $2.2B in 2015. OIP has grown and now has over 200 PDKs, 7500 technology files and 8500 IP blocks. The wafers enabled by this IP grew at a CAGR of 22% from 2005-14. Capex is up 10-16% from 2014 to about $10.5B to $11B, compared to $9.5B last year. Total capacity is 1.6M 8″ equivalent wafers per month, over 20,000 per day, up 12% year-on-year.

UPDATE: I totally messed up the title of this blog and the computation. It is over 50,000 wafers per day or over 200 per hour.

New processes are ramping faster than ever. N40 ramped in 35 months. N28 ramped in 22 months. N20 ramped in 3 months. N16 is ramping even faster. At this rate volume production will be faster than qual!

The second presentation was by Jack Sun, TSMC’s CTO. I tried to take notes on the processes but there was too much information. I’ll revisit this once I get some slides to work from. But in the meantime, here are a few highlights.

N10 will be risk production in Q4 of 2015. Development is on-track.
N7 will be risk production Q1 of 2017. SRAM test-chip is functional.
16FFC will be risk production in Q2 2016
16FF+ is in volume production, with a couple of dozen takeouts and 50 more expected before end of year

The key new process coming soon is 16FFC, which is the third generation of 16nm process. Speedup is 65% vs 28nm and 40% vs 20nm. Or a power saving for 70% vs 28nm or 60% vs 20nm. It can go down to 0.55V. TSMC have repeatedly stated that 16FFC will be a long-lived node, which I take to mean that 16FFC will be cheaper per transistor than N28. The design rules are the same so migrating designs and IP should be fairly straightforward. There is a new library coming that will allow operation down to 0.4V, with a focus on minimizing the non-gaussian variation.

N10 has a scale factor of 50% versus 16FF+, with a performance improvement of 20% or a power saving of 40%. There are 3 different Vt and gate-length bias covering a wide range of leakage/speed envelopes. N10 SRAM is yielding well, SERDES runs at 56Gbps with 22% better power efficiency than 16FF+.

N7 has a further speed improvement of 10-50% versus N10, or a power saving of 25-30%. It will be 1.6X the density. Risk production will be Q1 of 2017. Initially libraries for mobile, but new second generation libraries with taller cells for HPC. Special SRAM for HPC too, with 25% better performance. There is an ARM Cortex-A57 test chip showing 40-45% are reduction.

But the roadmap doesn’t end there. TSMC is doing research on Ge FinFET, III-V NFET, gate-all-around nanowires, 2D crystal, directed self-assembly, multi-e-beam direct write, inverse computational lithography. And, of course, EUV. TSMC have achieved 90W source power in-house. ASML have demonstrated 130W. They are working jointly to get all the settings worked out for 125 wafer/hour production.

Other segments. CMOS Image Sensor (CIS):

FSI front image sensor
BSI back image sensor (the die is thinned and the light comes through the back)
BSI/ISP back image sensor flipped onto an image signal processor
NIR near-infra-red

MEMS

accelerometer
pressure sensor
motion sensor
microphone
new gas sensors
new biometric sensors

Emerging new memories:

eRRAM
eMRAM

This is all from my handwritten notes. If you spot errors then correct me in the comments.

September 1, 2015August 22, 2024

SoC and Foundry Update 2H 2015!

SoC and Foundry Update 2H 2015!
by Daniel Nenni on 09-01-2015 at 10:00 pm
Categories: EDA, Foundries, GlobalFoundries, Samsung Foundry, TSMC

Rarely do I fly first class but I did on my recent trip to Asia. It was one of the new planes with pod-like seats that transforms into a bed. The flight left SFO at 1 A.M. so I fell asleep almost immediately missing the first gourmet meal. About half way through the flight I found myself barely awake staring straight up and what do I see? STARS! That has got to be one of the last things anyone wants to see while looking up on an international flight! Seriously, who puts fake stars on the ceiling of an airplane! EVA Airlines that’s who!

When I travel a lot of people want to meet with me to get the latest news from Silicon Valley. In exchange I get the latest news from wherever they are so it is a very nice quid pro quo type of thing, absolutely. The most common topics are the SoC and foundry business since they currently drive the semiconductor industry. Apple and Qualcomm are the most talked about SoC companies but Mediatek, Samsung, and even Intel are always discussed.

Let’s start with Apple: The big iProduct announcement is next week and we will finally get to see what is inside the iPhone 6s! Again, my bet is a Samsung based 14nm A9 SoC and inside the new iPads will be a TSMC based 16nm A9x SoC. I was right on the iPhone 5s (Samsung 28nm) and iPhone 6 (TSMC 20nm) so let’s see if I can keep my streak going. My bet is also that the Apple A9x will outperform all other SoCs and will continue to do so until mid to late next year.

Moving forward it is my bet that Apple will continue with TSMC 16nm for the iPhone7 with an enhanced version of the process specifically for Apple. Based on what I know today 10nm will not be in production in time for the iPhone 7 but could make it for the next iPads since iPads come out later in the year and require less volume. Currently Samsung and TSMC both have pre-production 10nm PDKs available but final decisions by the fabless elite have not been made. We should know more about where the fabless elite will fab 10nm at the end of this year. I would not expect 10nm production to start before Q2 2017 as there have been delays. The iProduct refresh in 2017 however will be 10nm for sure.

QCOM has a history of 2[SUP]nd[/SUP], 3[SUP]rd[/SUP], and even 4[SUP]th[/SUP] sourcing chip manufacturing down to 40nm. At 28nm everyone was forced into a monogamous relationship with TSMC which was very uncomfortable for a promiscuous company like QCOM. At 28nm QCOM is now in production at UMC and hopes to get ramped up at SMIC to appease the Chinese gods. QCOM as we have all heard will use both Samsung 14nm and GlobalFoundries 14nm for the next generation of Snapdragons. I’m also told that QCOM will use TSMC 16FF+ and they have a 14nm development agreement with SMIC in process.

Mediatek of course manufactures next door (literally) at TSMC and UMC and I do not see that changing anytime soon. Mediatek has hit semiconductor rock star status in Taiwan and they have attracted many ex TSMC and UMC employees. Not only does this give Mediatek leading edge design experience, it also gives them access to the inner foundry ranks. Given the importance of low power design for mobile I would bet Mediatek products will be FinFET enabled next year with the rest of the fabless elite so watch out QCOM!

I’m sorry, I ran out of space for more commentary. If you have questions we can continue the discussion in the comments section. Only registered SemiWiki members can read or write comments so if you are not already a SemiWiki member please join as my guest: https://www.legacy.semiwiki.com/forum/register.php

September 1, 2015August 22, 2024

TSMC is the Top Dog in Pure-Play Foundry Business

TSMC is the Top Dog in Pure-Play Foundry Business
by Pawan Fangaria on 09-01-2015 at 12:00 pm
Categories: Foundries, GlobalFoundries, TSMC

We all have echoed the fact that the arrival of fabless business model in the semiconductor industry has transformed it completely. The book, “Fabless: The Transformation of the Semiconductor Industry” provides several stories around that. In the backdrop of that, one key point to ponder upon is the start of pure-play foundries; TSMC being the initiator in 1987. The availability of pure-play foundries gave the boost and courage to small as well as large players around the world to start designs without owning fabs. The net result was a flood of fabless design companies and innovations in designs around the world. This is not without the pure-play foundries innovating themselves too. TSMC and subsequent foundries provided leading edge processes and technologies in manufacturing. Today, pure-play foundries provide manufacturing services not only to fabless companies but also to IDMs. Hence, looking at the other side of the coin, it would not be imprecise to say that the pure-play foundry model also transformed the semiconductor industry.

After TSMC, about ten more pure-play foundries were founded around the world, the latest being GLOBALFOUNDRIESin 2009. According to the first quarter sales figures of 2015, three pure-play foundries (TSMC, GLOBALFOUNDRIES, and UMC) occupy the ranks within top20 semiconductor companies in the world, TSMC being 3[SUP]rd[/SUP]. Interesting to note among the pure-play foundries is the following –

The percentage share of these top3 pure-play foundries clubbed together in the overall pure-play foundry sales is 79% and above; $33.68 B out of a total of $42.4 B in 2014, and $9.32 B out of a total of $11.4 B in 1Q 2015, i.e. 82%.

If we do a further analysis of TSMC’s share among the top20 pure-play foundries (i.e. the three foundries as stated above), it’s 74% in 2014 ($24.976 B out of $33.68 B) and 75% in 1Q 2015 ($6.995 B out of $9.318 B). What do we call TSMC in such a scenario?

Let’s also see the pure-play foundry business in recent perspective where we know TSMC had lost some business due to Samsungstarting in-house manufacturing of its Exynos and Appleallocating a part of their processors to Intel and Samsung. However, Apple is expected to come back to TSMC’s 16nm FinFET for their A9 processors in iPhone7. There are reasons for it; I’m not going in those details here. However, I would like to debate on how TSMC influences the overall pure-play foundry business. Let’s look at the following chart reported by IC Insights –

This chart depicts the usual trend of the best growth for pure-play foundries in Q2 every year (double-digit growth compared to Q1), i.e. ahead of Q3, the best quarter for total IC industry. However, in 2015 that trend was broken; in Q2 the sales declined slightly compared to Q1 instead of increasing as was seen in previous years. The reason – 5% decline in TSMC’s revenue in Q2 compared to Q1. If TSMC’s 5% change in revenue can change the pure-play industry trend, then that’s definitely the ‘Top Dog’ in the industry. Although there are competing technologies possessed by other foundries as well, I would go back to my hypothesis that business leadership along with technology leadership is the key to establish someone as the ‘Top Dog’.

For TSMC, rest of this year and 2016 are certainly looking better. IC Insights forecasts the overall pure-play foundry sales in Q4 2015 to reach over $12 B, the highest ever. The IC Insights pure-play foundry report is HERE for your reference.

Also read:
Changing Trends at the Top of Semicon Space. The chart in this article provides the sales numbers of the top3 pure-play foundries mentioned above.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

August 20, 2015

Older Nodes Get New Life With Ultra Low Power Variants for IoT

Older Nodes Get New Life With Ultra Low Power Variants for IoT
by Tom Simon on 08-20-2015 at 12:00 pm
Categories: EDA, General, IoT, Mobile, TSMC

Ever since I can remember, and I’ve been in EDA since the early 80’s, new process development has largely focused on the latest nodes. Trailing nodes were quickly put into support mode. New nodes benefited the most from static and dynamic voltage reduction efforts, as well as improvements in flows and performance. Only a small number of niche processes, usually produced by smaller captive fabs, were tuned over time for improvements. But the IoT has changed this.

With projected volumes for IoT chips in the billions, foundries, EDA and IP vendors have put a new emphasis on revisiting their offering for larger nodes. The biggest motivation for this is the need for lower power and the proliferation of wireless. When we say lower power, it’s not about needing fewer cooling fans, its about running for months on solar power, or making a wearable last for weeks before it needs to be recharged.

For wearables, using a larger battery is not an option. A typical wearable LiPo battery might have less than 20 milliamp-hours at 3.7V. Sleep modes need to be in the uA, not milliamp range. Every trick in the book is needed: voltage Islands, power islands, low leakage libraries, sub threshold operating voltages.

Apparently TSMC has been thinking about these issues for a while and concluded that updating processes alone will not solve the power problems faced by new products. So TSMC has announced the development of IoT platforms with several of their OIP partners. For its part TSMC is rolling out ultra low power (ULP) versions of its 0.18u, 90nm, 55nm, 40nm and 28nm processes. Several of them will come with embedded flash and the ability to support radio design.

TSMC expects the ULP processes to reduce operating voltages by 20% to 30%. That combined with standby power reductions promises to offer 2X to 10X increases in battery life.

TSMC has announced that the following partners are participating:

ARM – IoT subsystems for the Cortex-M and Cordio radio IP. Running on the 55nm ULP process, they can run below one-volt, saving significant power.

Cadence – Also targeting 55nm ULP, they offer Tensilica Fusion DSP’s for sensor and peripheral interfaces operating at optimal power levels. Tensilica cores are available for WiFi/IoT connectivity for wearables and other IoT applications. 40ULP and 28ULP are also available.

Dolphin Integration – Bringing ultra low power methodologies and flows for designing ultra low power designs that include voltage and power islands. They are providing tools to effectively reduce dynamic and static power for designs targeted by the TSMC partnership.

Imagination – IP for ultra low power designs. They are providing processor cores, wireless and other ancillary functions implemented as reference IoT subsystems. Imagination offers comprehensive IP for building a large number of IoT applications.

Synopsys – Working on an integrated IoT platform on TSMC’s 40nm ULP process. This will include a broad range of DesignWare IP. The highlights are the ultra low power ARC EM5D processor core, power and area optimized libraries, memory compilers, NVM as well as a number of IO and sensing blocks.

All of this represents a large commitment on the part of TSMC and their partners to create the processes and flow enablers necessary to fulfill projected design and volume demands fron the explosive growth of ultra low power connected designs for the IoT.

For more information on applications for different process nodes look on their site.

August 7, 2015

Is 7nm Coming to the TSMC OIP Ecosystem Forum?

Is 7nm Coming to the TSMC OIP Ecosystem Forum?
by Daniel Nenni on 08-07-2015 at 4:00 pm
Categories: FinFET, Foundries, TSMC

This is the 5[SUP]th[/SUP] TSMC Open Innovation Platform Ecosystem Forum and it is not to be missed. Please note that the location has moved from the San Jose Convention Center to the Santa Clara Convention Center which is literally right across the street from the new Levi’s Stadium. If you haven’t been to the new stadium you really should take a tour and stop by the SF 49ers Museum. Public tours run between 10am and 6pm and yes they have WiFi.

The new location will increase attendance significantly this year (my opinion) so you had better register now because space is limited. In addition to networking with 1,000+ semiconductor professionals you will get to hear from TSMC’s executives on what is new and improved for the different processes and surrounding ecosystem: 28nm, 16nm, 10nm, and I would bet 7nm will also be mentioned if not formally announced.

You may also get to hear from one of TSMC’s leading customers. At the TSMC Technology Symposium last April the guest speaker was Avago CEO Hock Tan. Since then Hock has engineered the acquisition of Broadcom for $37B. Previously he acquired LSI Logic for $6.6B so I would definitely like to hear a semiconductor industry update from an executive of his caliber, absolutely.

The event starts at 9am on Thursday, September 17[SUP]th[/SUP]. After the ninety minute executive presentations there are 30 technical papers divided into three tracks for EDA, IP, and Services. The paper abstracts are now up on the OIP website. And of course there will be a vendor expo with 80 vendors bearing gifts and the latest news on design enablement. Rumor has it Solido Design will be giving away the elite SemiWiki.com stylus penlights so you may want to go there first.

Click HEREfor the event overview, agenda and registration

|-
| 11:30 – 12:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Exploring Custom Metal Stacks for Advanced Node IC Design Using Early StarRC Extraction
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| align=”center” valign=”top” | Synopsys
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| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Migrating ARM Cortex-A53 designs From 28HPM to 28HPC+ – Getting Two Designs Out of a Single Implementation
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| align=”center” valign=”top” | ARM
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|-
| 12:00 – 13:00
| colspan=”3″ align=”center” valign=”top” | Lunch
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| 13:00 – 13:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Thermal and Color-aware Reliability Verification for Sub-16nm FinFET Designs
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| align=”center” valign=”top” | Ansys Inc.
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | High-Speed SerDes Design in Advanced TSMC Process: Architecture Implementation
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| align=”center” valign=”top” | GUC
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|-
| 13:30 – 14:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Custom Device Array- Place, Route, Simulate Prior to Layout
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| align=”center” valign=”top” | Cadence
|-

|-
| 14:00 – 14:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Hierarchical Fill Methodology for Advanced Nodes
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| align=”center” valign=”top” | Mentor Graphics
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|-
| 14:30 – 15:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | IC Packaging centric approach to design fanout-out WLCSP (InFO) designs
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| align=”center” valign=”top” | Cadence
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| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Rapid Implementation of IoT end-point sensor devices using ARM and TSMC IP
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| align=”center” valign=”top” | ARM
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|-
| 15:00 – 15:30
| colspan=”3″ align=”center” | Coffee Break
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| 15:30 – 16:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | 2-5X productivity improvement in converging to a DRC-clean cell design—Qualcomm’s experience with Calibre RealTime
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| align=”center” valign=”top” | Mentor Graphics
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|-
| 16:00 – 16:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Synopsys’ PrimeTime POCV Improve Productivity and PPA in FinFET Designs – NVIDIA Experience

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| align=”center” valign=”top” | Synopsys
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|-
| 16:30 – 17:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | TSMC Advanced Node EMIR analysis
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| align=”center” valign=”top” | Cadence
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|-
| 17:00 – 17:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | IC Compiler II key in accelerating time-to-market for HiSilicon’s next-generation 10-nm advanced SoC’s
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| align=”center” valign=”top” | Synopsys
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| 17:30– 18:30
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The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share real case solutions to today’s design challenges. Success stories that illustrate best practices in TSMC’s design ecosystem will highlight the event.

More than 90% of last year’s attendees said that “the forum helped them better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies to address your design challenges!

This year, the forum is a day-long conference kicking-off withtrend-setting addresses and announcements from TSMC and premier IC design company executives.

The technical sessions are dedicated to 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies, and an Ecosystem Pavilion feature up to 80 member companies showcasing their products and services.

Click HERE for the event overview, agenda and registration

July 18, 2015

TSMC (Apple) Update Q2 2015!

TSMC (Apple) Update Q2 2015!
by Daniel Nenni on 07-18-2015 at 8:00 pm
Categories: Foundries, TSMC

The TSMC quarterly conference call was last week and of course it stirred up quite a bit of controversy. Let me share with you my experience, observations, and opinions and maybe together we can come up with an accurate prediction for 2016. First let’s take a look at 20nm and what people now call the “Apple effect.”

Correct me if I’m wrong here but this is how I remember it: The TSMC 20nm process was highly criticized for cost, power leakage, and yield prior to the arrival of the Apple A8 and A8x SoCs. As we now know 20nm was the fastest ramping process in the history of TSMC and the A8 powered iPhone 6 is a huge success. This much is now well documented.

Next came TSMC 16nm. Unfortunately, the first 16nm process did not meet expectations of the fabless semiconductor ecosystem as compared to Intel and Samsung 14nm. Intel 14nm was faster and denser and Samsung 14nm was lower power. This was clearly a missstep for TSMC but they learned from it and came back with 16FF+ (second generation FinFETs) which is now the best performing process of its kind. TSMC openly makes this claim but I have confirmed it with several early access IP and fabless companies and they would know. 16FF+ based mobile products will hit the market in Q4 2015 and you will be impressed, absolutely.

TSMC 16FF+ does use the same BEOL (back end of line) as 20nm, which is the second half of the chip manufacturing process. The FEOL (front end of line) however is quite different. In fact, you will see a difference between the original TSMC 16nm and 16FF+ which has resulted in a significant PPA improvement (performance, power, and area). So when Morris Chang claims that 16FF+, which is technically their second generation FinFET, will be an even faster ramp than 20nm I believe it to be true.

As I predicted last year, Apple chose Samsung 14nm LPE for the iPhone6S (A9 SoC) and TSMC 16nmFF+ for the iPads (A9x). I stand by that prediction even though on the conference call Morris Chang said that in 2016 TSMC 16nm market share will be much greater than “our next competitors.” Given that Apple and QCOMM, TSMC’s two largest customers, are currently using Samsung 14nm there is really only one way this prediction can come true: Apple and QCOM will use 16FFC (TSMC’s third FinFET generation) for their SoCs in 2016.

TSMC also mentioned that 10nm will be in production in Q1 2017 which supports the above prediction that the iProducts released in 2016 will not be 10nm. The other interesting thing to note is the PPA numbers for 10nm: 15% speed gain at the same total power, or more than 35% power reduction at the same speed, and with k density of 2.2 times that of 16nm FinFET. I can tell you that Apple will not accept a 15% speed gain for a new process. I was told that the new 16FFC process due out mid 2016 was built “with” Apple so I would expect the same for 10nm. 16nm FF+ provides a 40% higher speed and 60% power savings over 20nm. My prediction is that the Apple version of 10nm for the 2017 iProducts will offer a minimum 25% speed increase.

Sound reasonable?

The conference call transcript is HERE.

July 11, 2015August 22, 2024

Who Needs to Lead at the 14, 10 and 7nm nodes

Who Needs to Lead at the 14, 10 and 7nm nodes
by Scotten Jones on 07-11-2015 at 12:00 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, Samsung Foundry, TSMC

IBM recently disclosed a working 7nm test chip generating a lot of excitement in the semiconductor industry and also in the mainstream media. In this article I wanted to explore the 14nm, 10nm and 7nm nodes, the status of the key competitors at each node and what it may mean for the companies.

Continue reading “Who Needs to Lead at the 14, 10 and 7nm nodes”