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TSMC: Semiconductors in the next ten years!

TSMC: Semiconductors in the next ten years!
by Daniel Nenni on 10-23-2017 at 6:00 am
Categories: Events, Foundries, TSMC
3 Comments

The TSMC 30th Anniversary Forum just ended so I will share a few notes before the rest of the media chimes in. The forum was live streamed on tsmc.com, hopefully it will be available for replay. The ballroom at the Grand Hyatt in Taipei was filled with cameras, semiconductor executives, and security personnel.

Here is the replay

The event started with a video about TSMC over the last 30 years followed by comments from Chairman Morris Chang. The keynotes were by Nvidia CEO Jensen Huang, Qualcomm CEO Steve Mollenkopf, ADI CEO Vincent Roche, ARM CEO Simon Segars, Broadcom CEO Hock Tan, ASML CEO Peter Wennink, and Apple COO Jeff Williams. Next was a panel discussion led by Chairman Morris Chang.

First let’s start with the jokes. Jensen Huang was supposed to go first but his presentation was not ready and Morris roasted him a bit over it. Jensen replied that it took him longer because he actually prepared for the event. Funny because it was a joke with a bit of truth to it because the other presentations were standard stock. Jensen did the best presentation which was all about AI which is in fact the future of semiconductors in the next ten years.

The best joke however was in response to a question about legal matters, if AI goes wrong who is held accountable? Morris pointed out that Steve Mollenkopf probably has the most legal experience of the group referring to Qualcomm’s massive legal challenges of late. Steve recused himself from the question of course. Even at 86 years old Morris still has a quick wit and provided most of the humor for the evening.

As I have mentioned before, AI will touch almost every chip we make in the coming years which will bring an insatiable compute demand that general purpose CPUs will never satisfy. This year Apple put a neural engine on the A11 SoC that’s capable of up to 600 billion operations per second. Nvidia GPUs do trillions of operations per second so we still have a ways to go for edge devices.

A couple of more interesting notes, the Apple-TSMC relationship started in 2010 which didn’t produce silicon until the iPhone 6 in 2014. Morris described the Apple-TSMC relationship as intense but Jeff Williams (Apple) said that you cannot double plan for the volumes of technology that Apple requires so partnerships are key. My take is that the TSMC-Apple relationship is very strong and will continue for the foreseeable future. Who else is going to be able to do business the Apple (non competing) way and still make big margins?

Jeff also predicts that medical will be the most disruptive AI application to which Morris agreed suggesting mediocre doctors will be replaced by technology. This is something I feel VERY strongly about. Medical care is barbaric by technology standards and we as a population are suffering as a result. Apple is focused on proactive medical care versus reactive which is what you see in most hospitals. Predicting strokes or heart events is possible today for example. AI enabled medical imaging systems is another example for tomorrow.

Security and privacy were discussed with Apple insisting that your data is more secure on your device than it is in the cloud. Maybe that’s why the new phones have a huge amount of memory (64-256 GB) while free iCloud storage is still only 5 GB. We use a private 1 TB cloud for just that reason by the way, our data stays in our possession. I certainly agree about security but privacy seems to be lost on millennials and they are the target market for most devices.

Bottom line: Congratulations to the TSMC support staff, this event was well done and congratulations to TSMC for an amazing 30 years. The room was filled with C level executives and a smattering of media folks like myself. It really was an honor to be there, being part of semiconductor history, absolutely.

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Reliability Signoff for FinFET Designs

Reliability Signoff for FinFET Designs
by Bernard Murphy on 10-17-2017 at 7:00 am
Categories: Ansys, Inc., Automotive, EDA, TSMC

Ansys recently hosted a webinar on reliability signoff for FinFET-based designs, spanning thermal, EM, ESD, EMC and aging effects. I doubt you’re going to easily find a more comprehensive coverage of reliability impact and analysis solutions. If you care about reliability in FinFET designs, you might want to check out this webinar. It covers a lot of ground, so much that I’ll touch only on aspects of thermal analysis here with just a few hints to the other topics. The webinar covers domains with products highlighted in red below.
Incidentally, ANSYS and TSMC are jointly presenting on this topic at ARM TechCon. You can get a free Expo pass which will let you into this presentation HERE.

Why is reliability a big deal in FinFET-based designs? There are multiple issues impacting aging, stress and other factors, but one particular issue should by now be well-known – the self-heating problem in FinFET devices. In planar devices, heat generated inside a transistor can escape largely through the substrate. But in a FinFET, dielectric is wrapped around the fin structure and, since dielectrics generally are poor thermal conductors, heat can’t as easily escape leading to a local temperature increase, and will ultimately escape significantly through local interconnect leading to additional heating in that interconnect.


Also, since FinFETs are built for high drive strength, they are driving more current through thinner interconnect resulting in more Joule heating. In addition to these effects, you have to consider the standard sources of heating, thanks to complex IP activity profiles in modern SoCs: active, idle, sleep modes and power off – all of which contribute to a heat map across the die which will vary with use-cases. Self-heating effects may contribute 5[SUP]o[/SUP] or more in variation and use-case effects may contribute 30[SUP]o[/SUP] or more across the die.

An accurate analysis has to take both these factors into account to meaningfully assess reliability impact. Typical margin-based (across the die) approaches are ineffective and lead to grossly uneconomic overdesign. Which of course would next take us into the big data and SeaScape topic but I’m not going to talk about that here. In this webinar Ansys’ focus is the reliability analysis.


The thermal reliability workflow starts with Totem-CTA for analysis of AMS or custom blocks. This is based on a transient simulation and library models to determine local heating, EM violations and FIT violations. Totem will also build a model for the block which you can then use in the next step.


RedHawk-CTA will analyze digital IPs and the full chip-package system in a power-thermal-electrical loop simulation to determine temperature profiles by use-case, along with thermal-aware EM and FIT violations. You probably know from my previous posts that it can also do this for 2.5D and 3D systems. Out of all of this, RedHawk-CTA tool will generate a model which can be used in system level analysis using Ansys IcePak, since system reliability concerns don’t stop at the package.

Ansys talks about a couple of customer case studies in the webinar where focus is very much on the additional complexity self-heating introduces to increasing FIT rates and how improved visibility into root causes can help manage these down to an acceptable level through local (modest impact) rather than global (high impact) fixes.

In other aspects of reliability, the webinar first touches on ESD and path finding. Again, both Totem and RedHawk provide support to aid in ESD signoff through resistance, current density, driver-receiver checks and dynamic checks. And out of this RedHawk (PathFinder) will also build a system-level model for system-level ESD analysis.

Electromagnetic compatibility (EMC) is an important component of reliability in part because many SoCs now have multiple radios. So it becomes important to analyze both for EMI (EM noise) and EMS (EM immunity). An interesting consequence of studies in this area is around the EMI impact of power switching in an SoC. We normally think of the impact of power switching on power noise, but also, unsurprisingly perhaps, power switching can create significant EMI spikes.

Finally the webinar covers analysis of aging effect using Path-FX. Aging is a hot topic these days. It’s important first to prove a design works correctly when built, within whatever margins, but what happens if behavior drifts over time, as it inevitably will, thanks to aging? One consequence can be that new critical paths can emerge, and therefore what were once safe operating conditions can become unsafe unless (in some cases) you slow the clock down. As a result, aging can create reliability problems. Since this aging won’t be uniform across the die, again you need detailed analysis to guide selective mitigation if you are going to avoid massive over-design.

That’s where Path-FX comes in; it simulates orders of magnitude faster than conventional circuit sim solutions, but still with Spice-level accuracy, using all design model, layout, parasitics and reliability PDKs from the foundry. From this you can compare the fresh design model critical paths with the aged model to find those paths where you need to take corrective design action.

Ansys really does seem to be in a class of its own in reliability analysis; I can see why they got a partner of the year award this year at TSMC. For anyone who cares about reliability tightly coupled with advanced foundry processes, they seem to be unbeatable. You can watch the webinar HERE.

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TSMC Teamwork Translates to Technical Triumph

TSMC Teamwork Translates to Technical Triumph
by Tom Simon on 10-02-2017 at 12:00 pm
Categories: Foundries, IP, Siemens EDA, Silicon Creations, TSMC

Most people think that designing successful high speed analog circuits requires a mixture of magic, skill and lots of hard work. While this might be true, in reality it also requires a large dose of collaboration among each of the members of the design, tool and fabrication panoply. This point was recently made abundantly clear at the TSMC Open Innovation Platform (OIP) Forum held in Santa Clara on September 13th. Indeed, the entire OIP ecosystem was established by TSMC to encourage this kind of collaboration. Over the years it has enabled significant advances in electronic product design and delivery.
Continue reading “TSMC Teamwork Translates to Technical Triumph”

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TSMC OIP and the Insatiable Computing Trend!

TSMC OIP and the Insatiable Computing Trend!
by Daniel Nenni on 09-14-2017 at 12:00 am
Categories: Foundries, TSMC

This year’s OIP was much more lighthearted than I remember which is understandable. TSMC is executing flawlessly, delivering new process technology every year. Last year’s opening speaker, David Keller, used the phrase “Celebrate the way we collaborate” which served as the theme for the conference. This year David’s catch phrase was “Insatiable computing trend” which again set the theme.

First up was Dr. Cliff Hou’s update on the design enablement for TSMC’s advanced process nodes. Cliff again hit on the Mobile, HPC, IoT and Automotive markets with a focus on 55ULP, 40ULP, 28HPC+, 22ULP/ULL, 16FFC, and 12FFC. Speaking of 16FFC, TSMC’s Fab 16 in Nanjing, China is on track to start production in the second half of 2018 approximately two years after the ground breaking. This will be the first FinFET wafers manufactured in China which is another first for TSMC. China represents the largest growth opportunity for TSMC so this is a very big deal.

Not surprisingly 10nm was missing from the presentations but as we all know Apple is shipping 10nm SoCs in the new iPads and iPhones. As you may have read, the new iPhone X supports the “Insatiable computing trend” but we can talk about that in more detail when the benchmarks and teardowns become available. Needless to say I will be one of the first ones on the block to own one.

Cliff made comparisons between 16nm and 7nm giving 7nm a 33% performance or 58% power advantage. 7nm is now in risk production with a dozen different tape-outs confirmed for 2017 and you can bet most of those are SoCs with a GPU and FPGA mixed in. 7nm HVM is on track for the first half of 2018 followed by N7+ (EUV) in 2019. N7+ today offers a 1.2x density and a 10% performance or 20% power improvement. The key point here is that the migration from N7 to N7+ is minimal meaning that TSMC 7nm will be a very “sticky” process. Being the first to EUV production will be a serious badge of honor so I expect N7+ will be ready for Apple in the first half of 2019.

Finally, Cliff updated us on TSMC’s packaging efforts: InFO_OS, InFO_POP, CoWos, and the new InFO_MS (integrated logic and memory). Packaging is now a key foundry advantage so we will be doing a much more detailed look at the different options in the coming weeks as the presentations are made available.

As you all know I’m a big fan of Cliff’s (having known him for many years) and he has never led me astray so you can take what he says to the bank, absolutely.

The other keynotes were done by our three beloved EDA companies who celebrated TSMC’s accomplishments over the last 30 years. I would give Aart de Geus the award for the most content without the use of slides. Aart offered a nice retrospective since Synopsys is also 30 years old so they really grew up together. Anirudh Devgan of Cadence talked about systems companies doing specialized chips to meet the need for their insatiable computing. As I mentioned before, systems companies now dominate SemiWiki readership so I found myself nodding my head quite a bit here. Wally Rhines gets the award for the funniest slide illustrating the yield improvements TSMC logos have accomplished over the years:

All-in-all it was time very well spent. It was a good crowd, the food was great, and I gave away another 100 books and SemiWiki pens in an effort to stay relevant. There were more than 30 technical papers that we will cover as soon as they are made available and if you have specific questions hit me up in the comments section.

Also read: TSMC Design Enablement Update

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Solido Debuts New ML Tool at TSMC OIP!

Solido Debuts New ML Tool at TSMC OIP!
by Daniel Nenni on 09-08-2017 at 7:00 am
Categories: EDA, Solido, TSMC

The TSMC OIP Ecosystem Forum is upon us and what better place to debut a new tool to prevent silicon failures. Solido Design Automation just launched its latest tool – PVTMC Verifier – and will be demonstrating it in their booth at OIP. This is the third product that was developed within its Machine Learning Labs and is available in their Variation Designer suite of products.

Request a Variation Designer demo here:

http://www.solidodesign.com/products/variation-designer/

I will be there as well during the breaks giving away books (Fabless: The Transformation of the Semiconductor Industry AND Mobile Unleashed), SemiWiki pens, and networking with the semiconductor elite, absolutely.

PVTMC Verifier solves a problem that anyone who’s had an unforeseen silicon failure knows well – PVT and statistical effects interact – but no one knew of a solution to this problem that wasn’t extremely expensive or take a long time to complete.

The brute force approach to address PVT+statistical variation requires hundreds of thousands or millions of simulations. For example, a typical netlist at 3 sigma with 45 PVT corners = 26.9K Monte Carlo samples * 45 corners = 1.2 million simulations. This is not possible to complete in a typical production timeframe. Alternatively, running PVT corners, then MC at the worst-case corner, is error prone because in many cases the worst-case PVT at nominal isn’t the worst-case PVT at your target sigma. Circuits would go to silicon where the failure would be found there, resulting in costly re-spins and increased design cycle time.

Using proprietary machine learning technologies, Solido PVTMC Verifier is able to provide brute force level PVT+statistical variation coverage in only 100’s to 1,000’s of simulations.. You load a netlist into the tool, specify the target sigma and PVT corners you want to test at, and PVTMC Verifier is able to fully verify your design across operating conditions and process variation.

Solido already has several of their customers using PVTMC Verifier in production. One large customer in the automotive space ran PVTMC Verifier on a chip that had already failed in silicon, and the tool correctly identified the failure in just 310 simulations where it previously required 10,000 brute-force Monte Carlo simulations. It replicated their silicon failure even though the customer thought it couldn’t be done.

A second IDM customer of Solido’s used PVTMC Verifier on a known problematic circuit with 9 environmental conditions where a failure was already found in silicon test but missed in simulation using their traditional variation-aware tools. They ran PVTMC Verifier and it also found the problem, and it took only 45 minutes (1,050 simulations). They then fixed the design, confirmed it was fixed in silicon, then re-ran PVTMC Verifier. The problem corner was no longer present. What this means is that PVTMC Verifier was fast enough to utilize for verification, it revealed variation problems before going to silicon, and it eliminated failure risk in the verification stage.

Solido PVTMC Verifier is also being utilized for automotive verification to higher sigma. A common flow involves quickly covering all PVT conditions at 5 sigma with PVTMC Verifier, then verifying the worst-case condition with Solido’s High Sigma Monte Carlo (HSMC) to tighten confidence intervals at the worst-case PVT.

Solido’s new PVTMC Verifier delivers unprecedented coverage of PVT and MC space. In the above case, it solved for 4.1 sigma statistical variation across all 45 PVT conditions. Brute-force Monte Carlo across all PVTs would deliver perfect accuracy but would have taken 45 million simulations. PVTMC Verifier is able to cover this full space using just 1,515 simulations.

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Breakfast with Aart de Geus and the Foundries!

Breakfast with Aart de Geus and the Foundries!
by Daniel Nenni on 09-06-2017 at 7:00 am
Categories: Arm, EDA, Foundries, GlobalFoundries, Samsung Foundry, Synopsys, TSMC

Being the number one EDA and the number one IP company does have its advantages and the resulting foundry relationships are a clear example. One of the DAC traditions that I truly enjoy is the Synopsys foundry breakfasts. Not only does Synopsys welcome scribes, they reserve a table up front for us and Synopsys CEO Aart de Geus has been known to join us for fresh fruit and candid conversations. Breakfast conversation with Aart is quite easy due to the wide range of topics he can speak to. Remember, Aart has his finger on the semiconductor pulse like no other. We had a very interesting chat about autonomous cars and of course an update on his band Legally Blue (my beautiful wife and I are fans).


The videos for the foundry breakfasts are up on the Synopsys website. The interesting thing about the foundry people is that their collective knowledge about the fabless semiconductor ecosystem is staggering. Take Willy Chen from TSMC for example, Willy has a masters degree in electrical engineering and more than 20 years experience, most of which are with TSMC . If I remember correctly, Willy started at TSMC in the PDK group and is now Deputy Director, Design Infrastructure Marketing. Bottom line: Willy sees more in a month than most of us do in a year, absolutely. Willy is also a very nice guy, a snappy dresser, and a great speaker, so definitely watch this first video:

Arm, Synopsys and TSMC kicked off DAC 2017 with an event to share the results of their collaboration to enable design on TSMC 16-nm and 7-nm process technology with the new Arm® Cortex®-A75 and Cortex-A55 processors and the Synopsys Design Platform. In this event video, they introduce the new Synopsys QuickStart Implementation Kits (QIKs) for the Arm cores that take advantage of Arm POP™ technology and Synopsys tools, and the collaborative design enablement for TSMC 16-nm and 7-nm process technology. HiSilicon concludes the video by describing their impressive mobile product success designed by taking advantage of the Arm/TSMC/Synopsys collaboration.

Collaborating to enable design with Arm’s latest processors (Cortex-A75, Cortex-A55), TSMC 16-nm and 7-nm processes and Synopsys’ Design Platform Watch the video replay

This next one features one of my favorite foundry people Kelvin Low. Unfortunately, Kelvin left the foundry business for IP and now works for ARM as Vice President of Marketing, PDG (Physical Design Group). So sadly this is the last you will hear from Kelvin on behalf of Samsung Foundry:

On June 20th of this year Samsung Foundry and Synopsys hosted a breakfast event and talked about their multi-year collaboration to develop the next-generation process nodes and enable advanced SoCs for the next wave of design innovation. Mamta Bansal, Sr. Director of Engineering at QUALCOMM delivered a spirited presentation on their use of Samsung Foundry 10nm node and Synopsys Design Platform tools for their recent design success.

“Relentless” multi year collaboration between Samsung Foundry and Synopsys enabling the next wave of design innovationWatch the video replay

The GLOBALFOUNDRIES breakfast was actually a dinner so my beautiful wife joined me. Greg Northrop is the featured guest speaker on this one. I had not met Greg before but his candid responses to questions were very enlightening. Greg spent 30+ years at IBM before joining GF as a Fellow in the Design Enablement Group so he knows where all of the dead technologies are buried, absolutely.

On June 20, 2017, Synopsys and GLOBALFOUNDRIES hosted a dinner event at DAC. Attendees heard how the two companies are collaborating on enablement of Synopsys’ design solutions and IP on GLOBALFOUNDRIES’ leading-edge dual roadmap process technologies.

Advanced Design Enablement and Ecosystem Readiness of GLOBALFOUNDRIES Dual Roadmap Technologies, Using the Synopsys Design PlatformWatch the video replay

All three videos are definitely worth your time….. If you want more commentary hit me up in the comments section.

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Apple iPhone Super Cycle Update!

Apple iPhone Super Cycle Update!
by Daniel Nenni on 09-01-2017 at 7:00 am
Categories: Foundries, Mobile, TSMC
34 Comments

In 2014 Apple released the iPhone 6 which included the first SoC built on a TSMC (20nm) process. This phone started what many call a “Super Cycle” of people upgrading. According to Apple, they now have more than 1 billion activated devices so this super cycle could be seriously super, absolutely.
Continue reading “Apple iPhone Super Cycle Update!”

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High Bandwidth Memory ASIC SiPs for Advanced Products!

High Bandwidth Memory ASIC SiPs for Advanced Products!
by Daniel Nenni on 08-30-2017 at 7:00 am
Categories: Open-Silicon, Semiconductor Services, TSMC

When someone says, “2.5D packaging” my first thought is TSMC and my second thought is Herb Reiter. Herb has more than 40 years of semiconductor experience and he has been a tireless promoter of 2.5D packaging for many years. Herb writes for and works with industry organizations on 2.5D work groups and events at conferences around the world. I have worked with Herb on various conferences and recommend him professionally at every opportunity.

Next month Herb is moderating a webinar with Open-Silicon on High Bandwidth Memory ASIC SiPs for High Performance Computing and Networking Applications on Tuesday, September 19, 2017 from 8:00 AM – 9:00 AM PDT. I strongly suggest you register today because this one will fill up!

This Open-Silicon webinar, moderated by Herb Reiter of eda 2 asic Consulting, Inc., will provide an overviewHBM2 ASIC SiPs (System in a Packages) for density and bandwidth-hungry systems based on silicon proven Open-Silicon’s High Bandwidth Memory (HBM2) IP subsystem solution. . Attendees will also learn about the system integration aspects of 2.5D HBM ASIC SiP, and performance results of various memory access patterns suiting different applications in High Performance Computing and Networking.

The webinar also summarizes silicon validation results of a 2.5D HBM2 ASIC SiP validation/evaluation platform, which is based on Open-Silicon’s HBM2 IP subsystem in TSMC’s 16nm in combination with TSMC’s CoWoSTM 2.5D silicon- interposer technology and HBM2 memory They will discuss the significance of the results and how they demonstrate functional validation and interoperability between Open-Silicon’s HBM2 IP subsystem and the HBM2 memory die stack. Attendees will learn about HBM2 memory and its advantages, applications and use cases.

The panelists will also discuss the HBM2 IP subsystem roadmap and Open-Silicon’s next generation multi-port AXI (Advanced eXtensible Interface) based HBM2 IP subsystem development targeting 2.4Gbps per-pin data rates, and beyond, in TSMC’s 7nm technology. This webinar is ideal for chip designers and system architects of emerging applications, such as high performance computing, networking, deep learning, neural networks, virtual reality, gaming, cloud computing and data centers…

For those of you who don’t know, TSMC’s CoWoS® (Chip-On-Wafer-On-Substrate) advanced packaging technology integrates logic computing and memory chips in a 3-D way for advanced products. CoWos targets high-speed applications such as: Graphics, networking, artificial intelligence, cloud computing, data center, and high-performance computing. CoWos was first implemented at 28nm in 2012 and continues today at 20nm and 16nm. Next up is 7nm which should be a banner node for CoWos, absolutely.

About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software, IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities.

The company has partnered with over 150 companies, ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 125 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. To learn more, visit www.open-silicon.com

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TSMC OIP Ecosystem Forum 2017 Preview!

TSMC OIP Ecosystem Forum 2017 Preview!
by Daniel Nenni on 08-23-2017 at 12:00 pm
Categories: FinFET, Foundries, TSMC
2 Comments

The TSMC OIP Ecosystem Forum is upon us again. I have yet to meet a disappointed attendee so it is definitely worth your time: Networking with more than 1,000 semiconductor professionals, the food, mingling with the 50+ EDA, IP, and Services Companies, the food, and of course the content. The 7nm and 7nm EUV updates alone are worth the trip, absolutely! And remember, it is September 13th at the very convenient Santa Clara Convention Center.

Continue reading “TSMC OIP Ecosystem Forum 2017 Preview!”

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Applying ISO 26262 in a Fabless Ecosystem – DAC Panel Discussion

Applying ISO 26262 in a Fabless Ecosystem – DAC Panel Discussion
by Tom Simon on 07-18-2017 at 12:00 pm
Categories: Automotive, Events, Imagination Technologies, Siemens EDA, TSMC

The fabless movement was instrumental in disaggregating the semiconductor industry. Vertical product development at the chip and system level has given way to a horizontal structure over the years. This organization of product development has been doing an admirable job of delivering extremely reliable products. However reliable for a phone is not reliable enough for an autonomous vehicle with a service life of up to and over a decade. This issue was recognized years ago and lead to the development of the ISO 26262 standard in 2011.

ISO 26262 deals with the electronic systems in a car, with the goal of avoiding systematic errors and faults, as well as helping to deal with random errors. It applies to non-critical systems such as infotainment and also to critical systems like brakes, steering and autonomous operation.

Electronic systems in cars are often produced by fables semiconductor companies and frequently incorporate 3[SUP]rd[/SUP] party IP. Applying ISO 26262 to products developed in a dispersed manner is leading to changes that are affecting every member of the supply chain. To explore these impacts Mentor hosted a panel discussion at DAC in Austin. The panel had representation from members of each element in the supply chain affected by ISO 26262.

At first glance it makes sense that Mentor would be on the panel as an embedded OS supplier, but in the context of ISO 26262, the design tool providers are also an essential link in the chain. Rob Bates, Chief Safety Officer for the Embedded Division, spoke on behalf of Mentor. Also on the panel was Volker Politz, VP Segment Marketing at Imagination Technologies, who talked about the changes necessitated for IP developers. Jim Eifert Automotive Architect at NXP provided insight from the automotive system integration perspective. Lastly, Lluis Paris, Director, Worldwide IP Alliance at TSMC shed light on how the foundries for fabless semiconductor companies have shifted the way they work in the automotive sector.

There was a round of introductory comments by each panelist. Jim from NXP said that a big benefit of the standard is that there is common terminology that buyers can use when speaking with suppliers. Lluis from TSMC talked about how the role of a fabless foundry has shifted from just supplying silicon to developing an automotive platform to enable and encourage ISO 26262. This stems from the need for more extensive sustaining engineering and additional product documentation among other things. TSMC has added the role of safety manager to their organization as part of this endeavor.

Volker from Imagination pointed out that now the IP provider is in the middle. In some ways they are partnered with their customer’s engineering department. Products fuse together external and internal IP and design work. The biggest change for him is that there is now a more formal way for them to work together. Rob from Mentor added that prior to ISO 26262 companies were just continuing to engage in their previous practices. The standard has really changed the way the companies involved operate. He cited the example of TSMC, who is rebuilding many aspect of how they deal with automotive designs from the ground up.

The first question put to the panel was, does IP have to be certified?

TSMC was quick to point out that IP does not have to be certified, but that the process for making the chip does. This arises because in many cases the applications for the IP are so large that the IP vendor can’t possibly know the use-case that is applicable. Imagination added that there is not really a certification for IP, but the vendors can help by delivering the necessary documentation with their IP. IP vendors can help contribute. NXP said that the car is what is certified, and the key is to turn over at each step of the development the correct documentation to facilitate this and create traceability.

The next question asked if embedded software should be considered IP.

Mentor responded by saying that the embedded software resides on the chip which is closer to the customer. Development tools are closely linked to the embedded code, so they too are tied to the standard in some way. NXP agreed that the embedded code needs to comply with the standard and wished there was more explicit requirements for development tools.

The next question asked if the car is ‘certified’ then what documentation is needed to create traceability up the chain from the components?

TSMC stated that the foundry has to do a larger number of things under ISO26262. These include special SPICE and reliability models, along with aging models. The car needs to be traceable after 18 years in case there is an issue down the road. The foundry needs to keep the process viable for a long time and may even potentially need to go back to the wafer info after many years. NXP added that the standard requires a quantitative approach to quality. As part of this it can go to the level of looking at parts per billion failure rates.

Mentor sees that ISO 26262 puts a burden on the tool users to qualify the tools they are using for design. However, realistically this is not something the tool users can take on by themselves. The tool vendor must play a role. This is why they created the Mentor Safe Program.

The panelists were asked, despite the increased level of work required, whether or not they saw benefits in following the process in terms of improved reliability and safety.

TSMC said that they were already doing many of the things that are needed. They feel that instead of a quality increase, what they are seeing is better lifecycle planning. Imagination answered by saying that they are seeing some improvements, but they are also seeing improved reusability. NXP followed by saying that their safety process was already working, but they now have a better documentation process. Mentor feels that the standard helps people look at what they were doing, and that it can only help.
Then came the question of how the standard should evolve. TSMC feels that the hardware side of the specification is comprehensive and stable. However, there is more work that will need to be done on the software side. Imagination would like to see more focus on real integrity. They feel it is important that people are committed to the process and this is the only way the data is reliable. They also expect additions in the area of security, which is at its core a safety issue. NXP amplified that concern by saying that security is absolutely a safety issue, and they are very concerned about hacking. Mentor also concurred that security is something that needs to be addressed more fully in the future versions of ISO 26262.

The panel closed with a question on what new things would be beneficial to the ecosystem. TSMC feels that there is a good ecosystem in place for silicon. They see further ecosystem work occurring in the customer infrastructure. Imagination reiterated the point that they felt that security should be a priority. Imagination said that the EDA companies can also do a lot to help. The more EDA players do – for instance fault injection – the easier it will be to meet the spec. NXP really wants to see chip level design flows made easier to qualify. If they can get a packaged solution it will reduce their need for spreadsheets.

Mentor agreed with this perspective and feels that EDA vendors can help make it possible to adhere to the standard more easily. For instance defect tracing analysis could be added, rather than it being an after-the-fact activity. Mentor sees value in adding capabilities to make it easier to qualify. At the end of the day Mentor feels these same practices and features have wider applicability. They want to move the process out of the automotive space. It could improve customer satisfaction in a wide range of products. Mentor did a great job of pulling together the panel participants and facilitating the discussion. With their Mentor Safe program, it is clear they are serious about automotive safety. For more information on Mentor’s work in this area, please look at their website.