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AMD Intel TSMC menage a trois and the trouble with trouples

AMD Intel TSMC menage a trois and the trouble with trouples
by Robert Maire on 11-01-2019 at 10:00 am
Categories: Foundries, Intel Foundry, Semiconductor Advisors, Semiconductor Services, TSMC
10 Comments

  • Its “Complicated”- A 3 way Chip Relationship
  • Competing for Wafers, Moore’s Law & Love
  • Who’s Competing with Whom?
  • All’s Fair

The 3 way relationship is more complex than it seems

On the surface it seems simple. AMD and TSMC compete with Intel making its own chips and TSMC making them for AMD. But below the surface the real competition is actually between Intel and TSMC for supremacy in Moore’s Law as that will determine chip performance, value and cost. Maybe not…Dig down another layer and maybe its a competition between the US and a foreign competitor. Dig a little deeper and its a clash of China versus the US.

So the competition is AMD  & China Versus Intel? Or is it? Could it be Intel & AMD versus TSMC? Could it be Intel & TSMC versus AMD? Maybe all three.

Falling down the rabbit hole

Everything seems simple until you ask who TSMC’s biggest customers are. You might answer with the obvious choices. Apple, Huawei, Qualcomm, AMD and who else? You might answer Nvidia or HiSilicon, Marvell, Broadcom, Mediatek as number 5 but what if Intel was a top customer of TSMC? Well that strange revelation may actually be the case TSMC has been making chips for Intel and Intel has been short of capacity.  Intel may be freeing up some capacity by off loading production to TSMC maybe a lot maybe a lot more.

A secret, convenient, affair?

Its not like either Intel or TSMC would want the “relationship” publicized. AMD might get mad at TSMC cheating behind their back and Intel might be embarrassed that it would have to go to its erstwhile competitor to get needed capacity…. much better to keep the “side” relationship quiet and discrete.

Is Intel really serious about Competing with TSMC?

Is Intel actually reducing “leading edge” capex?

On Intel’s recent conference call they spoke about wanting to get back on a 2 or 2.5 year Moore’s Law cadence after stumbling around for 5 years with the 14/10NM transition. Sounds good but they may not be putting their money where their mouth is?

Intel announced a $500M increase in Capex which sounds like a lot of money but in the scheme of things is really just a bit over 3% increase from their current Capex budget, a fairly paltry increase. More importantly Intel said on their call that a significant portion of their Capex was going to increase capacity.  We would interpret this “significant” capacity increase at likely more than 3% of their capex spend. The capacity increase is aimed more at 14NM and other non-leading edge geometries so the spend is not aimed at pushing Moore’s Law rather just making more of the same parts.

This suggests that the math means that actual Capex spend on 5NM and 7NM , leading edge, may actually be down after you take out the capacity spend.

This hardly seems like a way for Intel to get back on a 2 to 2.5 year Moore’s Law cadence let alone catch up to TSMC which had a huge (much bigger than 3%) increase in their capex.

So this begs the question if Intel is truly serious about catching TSMC… The numbers would indicate not… Maybe Intel really doesn’t want to compete…

Could Intel go “fab lite”? Shades of “real men have fabs” and Jerry Sanders at AMD

Maybe the financial math would be better for Intel to go fabless and throw its manufacturing to TSMC.  Its clearly working better than what they have done lately, Works for Apple. Has gotten AMD back in the race.

Maybe like Apple, AMD, Qualcomm and others you do the design and keep the IP and hand the dirty and capital intensive work to TSMC.

It would be funny to have both AMD and Intel CPUs made by TSMC….not a lot different from Apple and Huawei both getting their chips made by TSMC or Qualcomm and Broadcom or MediaTek and Marvell….. seems to be the model….

It begs the question that has been asked many times…why does Intel still have fabs?

Everybody is competing for TSMC’s love and capacity

People might say that Intel would never put itself in a position where it had to compete for capacity at TSMC versus AMD but the truth is that Intel is already there…just not at bleeding edge CPUs.  Apple is obviously TSMC’s favorite… Qualcomm always wants to keep a relationship with Samsung to keep TSMC honest and get more capacity.

Its like a bunch of teenagers fighting over who loves who more.  In this case, TSMC may be the object of everyone’s desire.

More plot twists & strange relationships than an opera

There are a lot of moving parts in these strange relationships. TSMC is a “frenemy” to Intel, Samsung is a “frenemy” to Apple.  All these are small sub-plots against the giant overarching drama between the US and China which desperately wants to take over both Taiwan and the Chip industry and they are both one and the same.  The trade war is a backdrop to the overarching drama.

Could Apple turn it into a four way drama?

What if Apple decides to dump Intel and X86 in favor of its own processors, for laptops and desktops, made by TSMC. Or could Apple go in the opposite direction and ask Intel to make its custom processors in Intel fabs in order to stamp them “Made in America” and avoid the China take over and IP risk? (not likely…but stranger things have happened..)

The risk factor in making almost every significant chip on the planet (other than Intel) on a small island an hour and a half sail away from China by one company seems strange when you think about it.

The stocks

Right now the drama continues to play out without a lot of definitive conclusions. We need to monitor Intel’s progress in both capacity and Moore’s Law and see if they can get it together.  Can AMD get the attention and capacity it needs form TSMC? Will Intel increase or decrease business with TSMC? What will happen with the trade war? When and how will Samsung come back? Will they give up on being a foundry?

Right now the best positioned company appears to be TSMC which sits at the nexus of the drama and is the friend that everyone wants to have which an enviable place to be. Intel is in wait and see mode and AMD has potential but needs to execute.

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TSMC Update Q3 2019 Absolutely!

TSMC Update Q3 2019 Absolutely!
by Daniel Nenni on 10-25-2019 at 6:00 am
Categories: Events, Foundries, TSMC
4 Comments

This will be a combination of the recent TSMC quarterly report, a look back at Cliff Hou’s keynote at the most recent TSMC conference, and conversations on SemiWiki.com. There has been a lot of press on this but of course the most important points are being missed. Semiconductors are complicated and getting more so, absolutely.

The big news out of the conference call was the increase in TSMC Capex from $12.5B to an even $15B which will be repeated in 2020 ($15B) and grow in 2021 due to increasing demand. Remember, TSMC closely partners with customers and builds capacity based on demand (wafer agreements) and not imagined demand like IDMS (Intel and Samsung).  On the technology side lets look at the opening statement from the transcript:

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO Now I will talk about our N5 and N3 status. Our N5 technology has already entered risk production with good yield. The N5 will adopt the EUV extensively and is well on track for volume production in the first half of next year. With 80%, 8-0, logic density gain and about a 20% speed gain compared with the 7-nanometer, our N5 technology is true full node stride from our N7. We believe it will be the foundry industry’s most advanced solution with the best density, performance and power until our 3-nanometer arrives. With N5, we are further expanding our customer product portfolio and increasing our addressable market. The initial ramp will be driven by both mobile and HPC applications. We are confident that 5-nanometer will have a strong ramp and be a large and long-lasting node for TSMC.

Daniel Nenni – Founder – SemiWiki.com LLC:. 5N may be considered a full node from 7N but not 6N (with an 18% density advantage over N7). In my opinion the 6nm node will be a VERY long lasting node and while 6N revenues will be lumped into 7N and 7N+, 6N revenue will rule all, my opinion.

5N and 3N will also share the same fabs as did 10N and 7N which will again speed HVM ramp and reduce development costs. It is the TSMC recipe to foundry success, absolutely.

According to a conversation on SemiWiki, N5 is said to be 30nm M2P and 50nm CPP with 6 tracks and 173MTx/mm2. This works out to ~1.8x denser than N7 which is what TSMC has said. Scott Jones is pretty sure M2P is ~ 30nm and 50nm for CPP which is what is needed to get the 1.8x density improvement they have discussed.

N5P was not mentioned but from what was discussed on SemiWiki N5P is the same design rules, just more strain, a performance enhancement. Apple requires a new process every year so this is it. N5P will be out in 2021 for the Apple iProduct refresh. I would expect more optimizations will be announced next year so you may see a density improvement based on better EUV or something like that.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: Our N7 process is the industry’s first commercially available EUV lithography technology. N7+ provide 15% to 20% higher density with improved power consumption when compared to N7. That is already in high volume production with yield similar to N7. We expect the strong demand for N7+ continue into next year and are increasing Capex to meet this demand for multiple customers.

Now N6. Our N6 provide a clear migration path for the second-wave N7 product as its design rules are 100% compatible with N7 while providing 18% logic density gain with performance-to-cost advantage. The N6 uses one more EUV layer than N7+. N6 risk production is scheduled to begin in first quarter next year with volume production starting before the end of 2020. We reaffirm 7-nanometer will contribute more than 25% of our wafer revenue in 2019 and we expect even higher percentage in 2020 due to worldwide development of 5G, accelerated demand from HPC, mobile and other application continue to grow.

Daniel Nenni – Founder – SemiWiki.com LLC: Remember, 7N/6N is 28N déjà vu all over again so there will be plenty of 6N capacity moving forward once Apple and the other mobile giants move to 5N. The big difference between 6N and 28N is that there will be no cheap knock-off processes from UMC and SMIC, not even close.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO Now I will talk about the N3. We are working with customers on N3 and the technology development progress is going well. Our N3 will be another full node from our N5 with PPA gain similar to the gain from N7 to N5. We expect our 3-nanometer technology will be the most advanced foundry technology in both PPA and transistor technology when it is introduced.

Daniel Nenni – Founder – SemiWiki.com LLC: TSMC N3 will again use FinFETs unlike Samsung who will use GAA which highlights the real difference between Samsung and TSMC. TSMC is focused on manufacturability versus bleeding edge technology. TSMC does not really have a choice here since they have the mobile giants (Apple, Huawei, etc…) pushing them for a new process node every year that can yield at a very high rate right out of the box. GAA will be 2nm for TSMC.

Packaging was also a focus of the call. We covered packaging and design enablement here:

A Future Vision for 3D Heterogeneous Packaging

A Review of TSMC’s OIP Ecosystem

Now for the relevant Q&A:

Gokul Hariharan – JP Morgan Chase & Co, Research Division – Head of Taiwan Equity Research and Senior Tech Analyst: So first of all, if we look at the history, whenever TSMC has had a step-up in CapEx, that is typically accompanied by a step-up in growth as well. So just wanted to kind of narrow down a little bit on the 5% to 10% growth, which is still kind of — the kind of growth that we were expecting when we were spending TWD 10 billion to TWD 11 billion. So could you give a little bit more details or maybe narrow down the forecast a little bit more for us? Because if we say a TWD 14 billion to TWD 15 billion range of CapEx, that’s closer to the high 30s or 40% capital intensity, higher than our previous range.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: Gokul, let me answer the question carefully. Let’s say that TSMC always build capacity, working closely with customer and to meet their demand. That’s our number one, okay? We discuss with the customer on their demand, we make our judgment also. Now we are increasing the CapEx quite a lot, no doubt about it. But then, that’s due to some of the reasons I can foresee for the future. First, the 5G’s ramp-up is much faster than 4G as we expected. Second, TSMC actually is expanding our customer portfolio, and in the same times, we’re also expanding our product portfolio. And so put all the factors together, we have a good reason that we increase our CapEx this year and probably next year.

Daniel Nenni – Founder – SemiWiki.com LLC: I was hoping packaging would come up in the Q&A. From the very beginning TSMC’s packaging efforts were looked at as a low margin business but it is also a VERY sticky business, much stickier than the wafer business. The mobile giants depend on packaging and they now “depend” on TSMC for packaging, absolutely.

Charlie Chan – Morgan Stanley, Research Division – Technology Analyst: Okay. And my next question is about the advanced packaging. I remember in the previous quarters, you commented advanced packaging should outgrow the front-end business. So first of all, is this remains the same trend? And also how about the potential margin dilution from the packaging business?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: The forecast on the advanced packaging business, the growth is — the growth rate is still faster than silicon growth rate. The wafer’s revenues growth rate stays the same, okay? Still that statement is still valid. The gross margin, that’s another consideration. The gross margin of the back-end business actually is lower today, still lower than the wafer margin. But we look at it whether it’s a good business to go or not on 2 factors. One, we really want to support our customer to improve their system performance. So we have to do it because of TSMC is the only one company right now who can support customers’ advanced packaging. Second actually is the CapEx intensity on the back end, and that’s advanced packaging business, is smaller. And so the asset turnover is better. So put all in all together, we still think it’s a very good business to pursue.

Daniel Nenni – Founder – SemiWiki.com LLC: As expected, the China question. TSMC’s China strategy started with Morris Chang many years ago and is nothing short of brilliant. Morris may or may not have seen the US-China trade riff coming but he positioned TSMC perfectly. TSMC has more than 400 active customers and more than 100 of those are now in China. In Q3 2019 China accounted for 20% of TSMC revenue, up from 15% last year. North America is -2% to 60%, EMEA is -1% to 6%, Asia Pacific is –1% to 9%, and Japan is -1% to 5%. I expect this trend to accelerate as the US and China continue to play economic politics.

Brett Simpson – Arete Research Services LLP – Senior Analyst: I had a question really on China. I guess in the last couple of years, we’ve seen the business double with Chinese customers. I guess at the moment, it’s pretty clear you’re going through a very healthy inflection point in the Chinese customers at the moment. So can you talk about how you see this part of the business evolving over the next 1 or 2 years? And then I guess from a planning perspective, are you concerned that the rise of your China business comes at the sacrifice of other customers, particularly U.S. companies?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: Well, we did see the strong course from China because that’s a very big market, especially in the semiconductor area. And we are happy to see that growth, and TSMC is offering the most leading-edge technology to support our customer in China. And so to be exact, we are going to grow with the China market. At the expense of other customer, the answer is no because we support all the customer with all our strength and our capacity.

Daniel Nenni – Founder – SemiWiki.com LLC: Interesting EUV question. I don’t remember TSMC publicly saying they made their own pellicle but of course we all knew. Yet another TSMC differentiation.

Roland Shu – Citigroup Inc, Research Division – Director and Head of Regional Semiconductor Research: Okay. And the second question is you announced that your EUV tools have been reached potentially maturity, but how about for the infrastructure? It means that for other component like photoresist, pellicle, photomask or even for this inspection tools, chemical and materials. So yes, we have — going to have a very fast ramp on 5-nanometer because of very strong demand from a customer, but are there any gating items for this EUV infrastructure will be potentially a risk?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: So far we do not see any gating item. All the infrastructure, actually TSMC, we are prepared. We have a — we produce our own pellicle. We have a large number of masking capacity and everything. So even photoresist, those kind of thing, we have been taking into account. So we are ready for the — actually, we are in a high-volume production for the EUV lithography technology. For next year, you have big — even higher volume, and I can assure you that we are all prepared.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: Okay. In TSMC, EUV lithography technology is now in the production stage. But are we happy with that? Not yet. We are still improving availability. We have output power of 250 watts, as we expected. Now we can operate the tool with 250 watts consistently. However, there’s still something that we need to improve so that we can improve the throughput, we can improve the availability so you can reduce the cost, continue to improve.

Daniel Nenni – Founder – SemiWiki.com LLC: And I’ll finish this blog with the lighter side of the Q&A. Remember this is live in front of an audience in Taipei and C.C. says this stuff with a straight face. It really is fun to watch:

Roland Shu – Citigroup Inc, Research Division – Director and Head of Regional Semiconductor Research: Okay. I think just a follow-up for — I know you don’t comment on the ASP, but for the same amount of the wafer shipment on N7+, is this going to contribute more revenue upside to TSMC?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: You just mentioned we don’t.

Roland Shu – Citigroup Inc, Research Division – Director and Head of Regional Semiconductor Research: No, I talk about revenue. I don’t talk about ASP.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: That’s the same thing.

Bruce Lu – Goldman Sachs Group Inc., Research Division – Research Analyst: That’s why I wanted you to give us some hint, right? We cannot just tell my investors that we have to trust TSMC. Even though I say that all the time but…

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: You can trust TSMC. No doubt about it.

Daniel Nenni – Founder – SemiWiki.com LLC: Absolutely!

Reference: https://www.tsmc.com/uploadfile/ir/quarterly/2019/3d36C/E/TSMC%203Q19%20transcript.pdf

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ASML – In Line Qtr but big bookings – Logic Strong! Memory ? EUV?

ASML – In Line Qtr but big bookings – Logic Strong! Memory ? EUV?
by Robert Maire on 10-20-2019 at 6:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services, TSMC

ASML in line QTR with big Orders
Near term slippage w long term upside
Logic is strong but memory recovery unknown
EUV is finally a reality/commercialized

In line quarter- supplier slippage expected in Q4
Results were revenues of Euro 3B and EPS of Euro 1.49, more or less in line with earnings estimate if a tad bit light in revenue. Outlook for Q4 is Euro 4B with 4 EUV systems slipping into 2020 due to supplier issues (now resolved)

Logic is leading the recovery… Obviously TSMC
Over 70% of orders are from foundry/logic customers as everyone is getting in the queue now that EUV is in commercial production. TSMC is the leader in real EUV and likely accounts for the largest portion of those future EUV orders

Memory still an unknown
Several months ago we said that the recovery would be led by logic as the memory recovery would take longer than most people expected due to the sidelined capacity amid excess supply and weak pricing.

This is becoming clearer to most people as we have heard from Micron, which was weaker than many expected and now clearly hearing from ASML that memory business remains weak with unknown timing of a recovery.
Some are expecting a recovery early in 2020, but we would not get our hopes up as it could take all of 2020 to get memory back on track.

Huge orders Euro 5B and 23 EUV tools
ASML is selling out its capacity very quickly as we are now seeing a virtual avalanche of orders. EUV has been proven and no customer wants to be excluded from the party or perhaps run out of capacity.

Part of the huge ramp is the large ramp in the numbers of layers in a chip made with EUV, going from a few ,like 3-5, going to 12 to 15 (depending upon whom you believe). Basically the number of tools has to increase proportionately with the number of layers. Memory is still a long way away from using EUV so in our view the current memory weakness, while impacting DUV and immersion is not slowing down EUV.

In a perverse way, the weakness in EUV demand for memory is likely of benefit to the logic side of the industry as it doesn’t compete for limited EUV tool availability.

40 plus EUV tools should be very easy to book for next year as we are more than halfway there. I think we can get there even without any memory recovery.

Not worried about supplier slippage
Given the complexity of an EUV tool and the huge supply chain we are certainly going to see issues here and there. The fact that its only a one quarter slip suggests its not a big or systemic problem.

We would likely take a longer term view as to the overall trend and worry less about the actual ship date and whether it falls within one quarter or another. ASML is not in a “turns” business like dep and etch or other relatively simple to assemble tools.

It down to production execution
As we are now past the milestone of actual commercial EUV production we are past the point of invention, luck, and pain and suffering trying to get the technology to work and more focused on production issues and the ramp of manufacturing.

To be sure, there are still many issues out there, pellicles, resist, reticle inspection, but what we have is working well enough to push forward on the number of layers using EUV and thus more tools.

We have covered ASML for almost 25 years with much of that history watching the EUV saga play out, so it is interesting to see the final conclusion (or perhaps beginning) of an era.

The stock –
Priced for perfection in an imperfect world, but still pretty good. ASML’s stock has steadily climbing based on the view of a recovering chip sector. Some stocks in the space have gotten a bit ahead of themselves but we think ASML’s value increase is justified given where we are with EUV, the strong logic/foundry demand and overall positioning in the market. Some investors may be unhappy with the slippage, but we are less concerned as you have to look at the longer term.

Some investors may be unhappy with a quarter that was just “in line” but given the memory weakness, we think “in line” is very good performance as ASML is working with one hand (memory) tied behind its back.

Overall we remain constructive on the stock and would look at pull backs or weakness as an opportunity to build or enhance a position going forward.
The stock is not cheap but the performance and positioning support the valuation.

We think that ASML has the lowest China/US trade problem exposure (though not zero) and EUV sales are less impacted by near term economic gyrations as the backlog is likely very strong. All in all a relatively defensive position in a very cyclical industry.

Summary
ASML remains a virtual monopoly, with a huge defensive moat, upside potential in revenues and margins and a leading technology position. We expect margins and therefore profitability to increase steadily as EUV ramps over the next few years leading to long term upside. It remains one of our top picks in large caps in the space.

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TSMC – Solid Q3 Beat Guide- 5G Driver – Big Capex Bump – Flawless Execution

TSMC – Solid Q3 Beat Guide- 5G Driver – Big Capex Bump – Flawless Execution
by Robert Maire on 10-19-2019 at 6:00 am
Categories: Foundries, Semiconductor Advisors, Semiconductor Services, TSMC
1 Comment

TSMC puts up solid QTR, Capex increase for 5NM and capacity increase, 5G/mobile remains driver- HPC good 7NM, 27% of revs- Very nice margins!

In line quarter-Good guide
TSMC reported revenues of $9.4B and EPS of $0.62 , more or less in line with expectations, perhaps a touch below ” whisper” expectations which had been growing along with the lead times for 7NM. Gross margin was a nice 47.6%.
Q4 is expected to be between $10.2B and $10.3B with gross margins between 48% and 50%. This revenue outlook is well above current street expectations.

Large bump up in Capex
We have been talking about a logic led recovery, in chip equipment, given the strength at TSMC. TSMC bumped up their 2019 capex from $12.5B to $14 to $15B with initial outlook for 2020 to be similar to 2019.

This suggests a bit of a hockey stick like capex spend in the current Q4 of 2019.This hockey stick will show up in a better than expected guide from tool companies

We think this is likely a strong mix of not only 5NM spend but also 7NM capacity related spend given better than expected demand and long lead times currently seen by customers.

Capex intensity, currently at 40% is expected to come down in 2020 and further come down in 2021 to 30% to 35%

5G and mobile remains the big upside in demand
In our view, customers in the mobile space are all rushing to get to market first with 5G devices to try to stake a claim to market share and early dominance. This has created a strong “land rush” of orders to insure enough 5G chips to power those devices.

7NM was 27% of total sales which supports this strong demand and suggests strong pricing ability as well.

This is quite a strong ramp from the start of 7NM earlier in the year. We are sure that HPC (read that as AMD) is also clearly helping to drive demand over the top.

Smartphone was 49% of revenue with HPC at 29%.

We don’t think any significant portion of sales was due to inventory build or channel stuffing as fears of trade ware related cut offs have subsided in the market.

TSMC winning on both yield and packaging
In our view, we think that TSMC is attracting more customers and thus the longer lead times as they have both better yields and better packaging technology.

We think Samsung has had more struggles with yield and coming up to speed despite (and potentially because of ) EUV implementation.

We also think that TSMC’s advanced capabilities in packaging allow it to offer customers more and better options in 2.5 and 3D packaging.

As customers look for other strategies outside of Moore’s law scaling, such as “chiplets”, these packaging options become a critical differentiating and enabling technology. Some customers, such as AMD, are currently banking on advantages of a “chiplet” architecture.

Collateral impact on equipment companies
TSMC’s report , and large capex increase, confirms our view that there is a strong near term pick up in equipment demand despite memory “sucking wind”.

We think most equipment suppliers will report at least in line or likely better than expected results in the current quarter but more importantly will guide even higher going forward as orders from TSMC hit their order books.

This is very much in line with our “logic/foundry led recovery” that we have talked about for several months. While not a rip roaring semicap recovery, its better than the bouncing along the bottom that the industry has been stuck with and importantly puts an upward bias on business even though the slope may be low without memory.

The Stock – Nice quarter, but perhaps not up to the unrealistic expectations of the market
Its clear that chip stocks have been on a tear and along with the stocks, and so have expectations. Much of this in TSMC’s case is a combination of Apple talking about increasing supplier orders by 10% along with the extended lead times at TSMC 7NM. We think expectations and the stock both got a little bit ahead of themselves such that when the company reported an excellent quarter, such as it did, that investors were unimpressed as it didn’t blow away numbers.

We would use any weakness as an entry point to add to positions in TSMC.

They are now more dominant in foundry than ever before and if anything they are lengthening their lead over number two Samsung. Near term demand looks very good, margins are good and getting better.

Most importantly, TSMC continues to push Moore’s Law forward without any visible hiccups or delays…..perhaps they make it look too easy…..perhaps they should have a one quarter “oops” to make them look human and reset investors expectation of perfect performance in technology execution.

They have a very long runway of upside in 5G , with little competition, ahead of them. They are also the “real” engine behind AMD’s success and will get their fair share of the upside associated with that and other HPC business.

We like companies that have dominant or monopolistic-like positions, great execution on technology with a strong defensive “moat” . All this usually combines to show up in financial performance and future upside which we clearly have with TSMC.

We continue to be a buyer of the stock and would be more aggressive on pullbacks. Our only significant cautions would be trade and macro economic risk that all chip companies share.

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My Top Three Reasons to Attend IEDM 2019

My Top Three Reasons to Attend IEDM 2019
by Scotten Jones on 10-11-2019 at 6:10 am
Categories: Events, FD-SOI, FinFET, Foundries, Intel Foundry, TSMC

The International Electron Devices Meeting is a premier event to learn about the latest in semiconductor process technology. Held every year in early December is San Francisco this years conference will be held  from Decembers 7th through December 11th. You can learn more about the conference at their web site here.

This is a must attend conference for me every year.

The following are a few of the announced papers I am particularly excited about:

(1) TSMC to Unveil a Leading-Edge 5nm CMOS Technology Platform: TSMC researchers will describe a 5nm CMOS process optimized for both mobile and high-performance computing. It offers nearly twice the logic density (1.84x) and a 15% speed gain or 30% power reduction over the company’s 7nm process. It incorporates extensive use of EUV lithography to replace immersion lithography at key points in the manufacturing process. As a result, the total mask count is reduced vs. the 7nm technology. TSMC’s 5nm platform also features high channelmobility FinFETs and high-density SRAM cells. The SRAM can be optimized for low-power or high-performance applications, and the researchers say the high-density version (0.021µm2) is the highest-density SRAM ever reported. In a test circuit, a PAM4 transmitter (used in highspeed data communications) built with the 5nm CMOS process demonstrated speeds of 130 Gb/s with 0.96pJ/bit energy efficiency. The researchers say high-volume production is targeted for 1H20. (Paper #36.7, “5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and HighMobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing Applications,” G. Yeap et al., TSMC)

(2) Intel Says Heterogeneous 3D Integration Can Drive Scaling: CMOS technology requires both NMOS and PMOS devices, but the performance of PMOS lags NMOS, a mismatch which must be addressed in order to wring every last bit of performance and energy efficiency from future chips. One way to do that is to build PMOS devices with higher-mobility channels than their NMOS counterparts, but because these are built from materials other than silicon (Si) which require different processing, it is challenging to build one type without damaging the other. Intel researchers got around this with a 3D sequential stacking architecture. They first built Si FinFETNMOS transistors on a silicon wafer. On a separate Si wafer they fabricated a single-crystalline Ge film for use as a buffer layer. They flipped the second wafer, bonded it to the first, annealed them both to produce a void-free interface, cleaved the second wafer away except for the Ge layer, and then built gate-all-around (GAA) Ge-channel PMOS devices on top of it. There was no performance degradation in the underlying NMOS devices, and in an inverter test circuit the PMOS devices demonstrated the best Ion-Ioff performance ever reported for Ge-channel PMOS transistors (Ion=497 µA/µm and Ioff=8nA/µm at 0.5V). The researchers say these results show that heterogeneous 3D integration is promising for CMOS logic in highly scaled technology nodes. (Paper #29.7, “300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low-Power, High-Performance Logic Applications,” W. Rachmady et al., Intel.)

(3) Versatile 22nm STT-MRAM Technology: Many electronics applications require fast nonvolatile memory (NVM), but embedded flash, the current dominant technology, is becoming too complex and expensive to scale much beyond 28nm. A type of embedded NVM known as STT-MRAM has received a great deal of attention. STT-MRAM uses magnetic tunnel junctions (MTJs) to store data in magnetic fields rather than as electric charge, but this ability decreases as temperature increases. That makes STT-MRAM both challenging to build – it is fabricated in a chip’s interconnect and must survive high-temperature solder reflow – and also to use in applications such as automotive, where thermal specifications are demanding and the ability to resist outside magnetic fields is critical. TSMC will describe a versatile 22nm STT-MRAM technology that operates over a temperature range of -40ºC to 150ºC and retains data through six solder reflow cycles. It demonstrated a 10-year magnetic field immunity of >1100 Oe at 25ºC at a 1ppm error rate, and <1ppm when in a shield-in-package configuration. The researchers say that by trading off some of the reflow capability and using smaller MTJs, even higher performance can be achieved (e.g., 6ns read times/30ns write times), making them appealing for artificial intelligence inference engines. (Paper #2.7, “22nm STT-MRAM for Reflow and Automotive Uses with High Yield, Reliability and Magnetic Immunity and with Performance and Shielding Options,” W. Gallagher et al., TSMC)

About IEDM
With a history stretching back more than 60 years, the IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. The conference scope not only encompasses devices in silicon, compound and organic semiconductors, but also in emerging material systems. IEDM is truly an international conference, with strong representation from speakers from around the globe.

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A Future Vision for 3D Heterogeneous Packaging

A Future Vision for 3D Heterogeneous Packaging
by Daniel Nenni on 10-07-2019 at 6:00 am
Categories: Events, Foundries, TSMC
3 Comments

At the recent Open Innovation Platform® Ecosystem Forum in Santa Clara, TSMC provided an enlightening look into the future of heterogeneous packaging technology.  Although the term chiplet packaging is often used to describe the integration of multiple silicon die of potentially widely-varying functionality, this article will use the term heterogeneous packaging.  The examples below illustrate integration of both large and small die, DRAM die, and a full high-bandwidth memory die stacks (HBM2), much richer in scope than would commonly be designated as a chiplet.  Dr. Douglas Yu, Vice President of Integrated Interconnect and Packaging at TSMC, provided a review of current TSMC heterogeneous packaging offerings, and a 3D package vision that could be best described as “More-than-More-than-Moore”.

Doug began with the well-understood realization that the pace at which the cost-per-transistor has improved with IC process technology scaling has slowed.

Figure 1.  The rate of cost-per-transistor improvements with process technology scaling has slowed.  (Source:  TSMC)

There are certainly ongoing product PPA benefits to scaling, but the ultimate cost for the total system functionality may drive system designers to pursue heterogeneous packaging alternatives.

CoWoS

The first heterogeneous packaging offering from TSMC was Chip-on-Wafer-on-Substrate ( CoWoS® ).  A cross-section of a CoWoS® package is illustrated below.

Figure 2.  CoWoS® package integration  (Source:  TSMC)

A silicon interposer provides the interconnects between the die, with through-silicon vias (TSV) to the substrate below.  Doug highlighted the recent advances in CoWoS® technology in production, specifically the ability to fabricate the interposer at 2X the max reticle size for wafer lithography.

Figure 3.  CoWo®S support for a silicon interposer greater than the single max-reticle size   (Source: TSMC)

InFO-PoP

Doug reviewed TSMC’s cost effective heterogeneous integration package, based on the Integrated FanOut (InFO) technology.  The original InFO offering provided (reconstituted) wafer-level redistribution layer connectivity to extended bump locations outside the die perimeter.  The newer InFO-PoP package cross section is illustrated below.

Figure 4.  InFO-PoP cross section  (Source:  TSMC)

The extension of the InFO molded package beyond the embedded die is used for Through-InFO vias (TIV) between the top die and the redistribution layer connections.

SoIC®

A more recent TSMC heterogeneous package innovation involves the transition from microbump connections between die and substrate to a bumpless (thermo-compression) bond between direct die connections – see the figure below for a comparison between microbump and bumpless attach. TSMC-SoIC® is an innovative frontend wafer-process-based platform that integrates multi-chip, multi-tier, multi-function and mix-and-match technologies to enable high speed, high bandwidth, low power, high pitch density, and minimal footprint and stack-height heterogeneous 3D IC integration.

Figure 5.  Comparison of bump and bumpless technology characteristics, and SoIC® package cross-section  (Source:  TSMC)

Through silicon vias provide connection to bumps, part of the final back-end package assembly flow.  The density and electrical characteristics of the bumpless attach technology are far superior.  (Here’s a previous semiwiki article that describes the TSMC SoIC® package technology – link.)

https://semiwiki.com/semiconductor-manufacturers/tsmc/8150-tsmc-technology-symposium-review-part-ii/

Future Vision

Doug provided a vision for heterogeneous packaging, which combines the unique advantages of the technologies described above.  The figure directly below depicts a bumpless SoIC® composite as part of a larger InFO or CoWoS® package, integrating additional die and/or HBM memory stacks.

The second figure below illustrates multiple levels of (thinned) die using bumpless attach for subsequent back-end package assembly.  Doug referred to this multi-level SoIC® solution as part of the transition from 3D system integration to full 3D system scaling.

Figure 6.  SoIC® integration in a subsequent InFO or CoWoS® package  (Source:  TSMC)

Figure 7.  Multi-level bumpless die integration à 3D system scaling  (Source:  TSMC)

The heterogeneous packaging technology vision presented by TSMC will truly provide system architects with great opportunities for continued scaling.  In addition to traditional monolithic die PPA considerations for technology selection, this vision offers additional opportunities for system-level functional integration and packaging cost optimizations.  It will be fascinating to see how these heterogeneous packaging offerings impact future system designs.

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A Review of TSMC’s OIP Ecosystem

A Review of TSMC’s OIP Ecosystem
by Daniel Nenni on 10-06-2019 at 10:00 am
Categories: Events, Foundries, TSMC
1 Comment

Each year, TSMC conducts two events – the Technology symposium in the Spring and the Open Innovation Platform (OIP) ® Ecosystem Forum in the Fall.  Yet, what is the OIP ecosystem?  What does it encompass?  And, how does the program differentiate TSMC from other foundries?  At the recent OIP Forum in Santa Clara, Suk Lee, Senior Director, TSMC Design Infrastructure Management Division, presented a review of OIP, highlighting the breadth of technology and support available for TSMC process nodes.  Additionally, and very significantly, he described the extensive engineering investment made to develop and qualify new process design kit materials (PDK) and IP offerings.  Here are some of the highlights of Suk’s presentation.

Figure 1.  OIP partner overview  (Source:  TSMC)

OIP entails the collaboration between TSMC and numerous partners, spanning a range of technical facets of silicon foundry support:

  • EDA tool providers
  • IP developers
  • Design Center Alliance (DCA) providers, offering services ranging from system-level front-end design to back-end physical/test implementation
  • Value Chain Aggregators (VCA), additional service providers commonly offering a different set of capabilities, including assembly/test and supply chain management support

and, the newest aspect of OIP partnership, which was announced last year with the introduction of its OIP Virtual Design Environment (OIP VDE), lowering entry barriers of Cloud adoption for the customers of all sizes

  • Cloud service providers

To perhaps better distinguish between the DCA and VCA partners, Suk overlaid the previous chart on top of the Design Enablement and Process Development groups at TSMC – see the figure below.

 Figure 2.  OIP partner interactions with TSMC R&D  (Source:  TSMC)

Yet, these OIP designations are much more than companies enrolling with TSMC.  Suk emphasized the qualification requirements and ongoing monitoring to which each OIP partner is subjected, as illustrated below.

Figure 3.  Examples of OIP partner qualification requirements  (Source:  TSMC)

From TSMC’s own derivative of ISO9000 qualify management and assurance (aka, TSMC9000) to qualification of process interconnect technology definitions to ongoing certification of OIP service providers, there is a major emphasis on ensuring foundry customer success.

Perhaps the best illustration of OIP collaboration is the activity pursued with EDA partners during new process development.  This activity ensures new tool features and full methodology reference flow capabilities are qualified concurrently with initial process availability for IP developers and early end customer adopters.  Suk provided examples where new EDA tool attributes were defined, developed, and integrated into reference flows, driven by both process innovations (e.g., EUV lithography) and design reliability and manufacturability (e.g., via pillars, statistical analysis).  The figures below illustrate how the digital and custom design flows from EDA OIP partners were enhanced in support of these advanced process requirements.

Figure 4.  New EDA tool features addressing process requirements – digital flows  (Source:  TSMC)

Figure 5.  New EDA tool features addressing process requirements – custom implementation flows  (Source:  TSMC)

Engineers are skeptical by nature, seeking a silicon-proven demonstration of models, EDA tool features, and reference flows.  Suk highlighted the specific collaboration with ARM – for nearly a decade, TSMC and ARM have used leading ARM core IP as a testchip vehicle.  Full EDA (and IP) qualification reports are available at TSMC’s customer portal. On the day of OIP Forum, the two companies also announced the latest result of their collaboration, an industry-first 7nm silicon-proven chiplet system based on multiple Arm® cores and leveraging TSMC’s Chip-on-Wafer-on-Substrate (CoWoS®) advanced packaging solution.

 

Figure 6.  Screenshot of example EDA qualification reports on the TSMC portal   (Source:  TSMC)

With all the news relative to new process node announcements, it is easy to overlook the underlying activities and resources required to synchronize process availability with the companies supporting the related EDA, IP, and service provider ecosystem.  Suk’s presentation reminded the OIP Ecosystem Forum audience of the tremendous investment made as part of the effort to sustain Moore’s Law (for at least another node or two).  The focus that TSMC has applied to design enablement has truly been a differentiating characteristic of their corporate philosophy.

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TSMC OIP Overview and Agenda!

TSMC OIP Overview and Agenda!
by Daniel Nenni on 09-05-2019 at 6:00 am
Categories: Events, Foundries, TSMC

The TSMC Symposium and OIP Ecosystem Fourm are the most coveted events of the year for the fabless semiconductor ecosystem, absolutely. In my 35 years of semiconductor experience never has there been a more exciting time in the ecosystem and that is clear by the overview and agenda for this year’s event. I hope to see you there:

The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share practical, tested solutions to today’s design challenges. Success stories that illustrate TSMC’s design ecosystem best practices highlight the event.

More than 90% of last year’s attendees said that, “the forum helped me better understand TSMC’s Open Innovation Platform” and that “I found it effective to hear directly from TSMC OIP member companies.”

This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies and joint design solutions to address your design challenges in High-Performance Computing (HPC), Mobile, Automotive and Internet-of-Thing (IoT) applications.

This year, the forum is a day-long conference kicking-off with trend-setting addresses and announcements from TSMC and leading IC design company executives.

The technical sessions are dedicated to 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies. And the Ecosystem Pavilion feature up to 70 member companies showcasing their products and services.

Date: Thursday, September 26, 2019 8:00 AM – 6:30 PM

Venue: Santa Clara Convention Center

Learn About:

  • Emerging advanced node design challenges including 5nm, 6nm, 7nm, 12FFC/16FFC, 16FF+, 22ULP/ULL, 28nm, and ultra-low power process technologies.
  • Updated design solutions for specialty technologies supporting Internet-of-Thing (IoT) applications
  • Successful, real-life applications of design technologies and IP from ecosystem members and TSMC customers
  • Ecosystem-specific TSMC reference flow implementations
  • New innovations for next generation product designs targeting HPC, mobile, automotive and IoT applications

Hear directly from ecosystem companies about their TSMC-specific design solutions. Network with your peers and more than 1,000 industry experts and end users.

The TSMC Open Innovation Platform Ecosystem Forum is an “invitation-only” event.  Please register to attend. We look forward to seeing you at the event.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.

Agenda:

Join the TSMC 2019 Open Innovation Platform® Ecosystem Forum and hear directly from TSMC OIP companies about how to leverage their technology to your design challenges!

08:00 – 09:00 Registration & Ecosystem Pavilion

09:00 – 09:20 Welcome Remarks

09:20 – 10:10 TSMC and its Ecosystem for Innovation

10:10 – 10:30 Coffee Break

REGISTRATION

Please click the paper title to see its abstract:
HPC & 3DIC Mobile & Automotive IoT & RF
10:30 – 11:00
TSMC 3DIC Design Enablement Updates
TSMC
TSMC EDA & IP Design Enablement Updates
TSMC
TSMC RF Design Enablement Updates
TSMC
11:00 – 11:30

Calibre in the Cloud – A Case study with AMD, Mentor & TSMC
Microsoft/AMD/Mentor

Functional Safety Analysis and Verification to meet the requirements of the Automotive market
Texas Instruments/Cadence

Simplify Energy Efficient designs with cost-effective SoC Platform
Dolphin Design
11:30 – 12:00

Optimizing FPGA-HBM in InFO_MS Structure
Xilinx/Cadence

Thermal-induced reliability challenge and solution for advanced IC design
ANSYS

Flexible clocking solutions in advanced FinFET processes from 16nm to 5nm
Silicon Creations
12:00 – 13:00 Lunch & Ecosystem Pavilion
13:00 – 13:30

Chiplets solutions using CoWoS and InFO with 112Gbps SerDes and HBM2E/3.2Gbps for AI, HPC and Networking
GUC

Overcome time-to-market and resource challenges: Hierarchical DFT for advanced node SoC design and production
AMD/Mentor

Developing AI-based Solutions for Chip Design
Synopsys
13:30 – 14:00

Realizing Adaptable Compute Platform for AI/ML and 5G with Synopsys’ Fusion Design Platform
Xilinx/Synopsys

Comprehensive ESD/Latch-up reliability verification for IP & SoC Designs
NXP/Silicon Frontline/Mentor

Reliable, Secure and Flexible OTP solutions in TSMC for IoT, AI and Automotive Applications
eMemory
14:00 – 14:30

HBM2E 4gbps I/O Design Techniques in 7nm & Below Nodes
Open-Silicon

Sensor fusion and ADAS SOC designs in TSMC 16FFC and N7
Cadence

High-Speed Interface IP PAM-4 56G/112G Ethernet PHY IP for 400G and Beyond Hyperscale Data Centers
Synopsys
14:30 – 15:00

Pushing 3GHz Performance of TSMC N7 Arm Neoverse N1 CPU using the Cadence Digital Flow
Cadence/Arm

AWS Cloud enablement of design characterization flows using Synopsys® Primetime® & HSPICE®
Xilinx/Synopsys

Automotive IP Functional Safety – A Verification Challenge
Cadence
15:00 – 15:30 Coffee Break & Ecosystem Pavilion
15:30 – 16:00

Large Scale Silicon Photonic Interconnects for Mass Market Adoption
HPE/Mentor

A New Era of MIPI D-PHY and C- PHY: Automotive Applications
M31

Best practices for Arm Cortex CPU energy efficient implementation flows
Arm
16:00 – 16:30

Photonics Coming of Age: From Laboratory to Mainstream Applications
Cadence/Lumerical

Integrating ADAS Controllers with Automotive-Grade IP for TSMC N7
Synopsys

The Challenges Posed by Dynamic Uncertainty on AI & ML Devices Targeting 16nm, 7nm & 5nm
Moortec
16:30 – 17:00

Accelerating Semiconductor Design Flows with EDA on the Cloud
Astera Labs/AWS

Arm automotive physical IP addresses new feature and functionality demands
Arm

Developing AI Accelerators for TSMC N7
Synopsys
17:00 – 17:30

Best Practices using Synopsys Fusion Technology to Achieve High-performance, Energy Efficient implementations of the latest Arm® Processors in TSMC 7nm FinFET Process Technology
Synopsys/Arm

Cloud-based Characterization with Cadence Liberate Trio Characterization Suite and Arm-based Graviton
Cadence
Optimize SOC designs while enabling faster tapeouts by closing chip integration DRC issues early in the design cycle
MaxLinear/Mentor
17:30– 18:30 Social Hour

 

TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s largest dedicated semiconductor foundry ever since. The company supports a thriving ecosystem of global customers and partners with the industry’s leading process technology and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry.

TSMC serves its customers with annual capacity of about 12 million 12-inch equivalent wafers in 2019 from fabs in Taiwan, the United States, and China, and provides the broadest range of technologies from 0.5 micron plus all the way to foundry’s most advanced processes, which is 7-nanometer today. TSMC is the first foundry to provide 7-nanometer production capabilities, and is headquartered in Hsinchu, Taiwan.

REGISTRATION

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TSMC in the Cloud Update #56thDAC 2019

TSMC in the Cloud Update #56thDAC 2019
by Daniel Nenni on 06-13-2019 at 10:00 am
Categories: Events, Siemens EDA, TSMC
2 Comments

During my Taiwan visit, prior to Las Vegas, I was fortunate to spend time with Willy Chen and Vivian Jiang to prepare for the cloud panel I moderated at #56thDAC. Willy and Vivian are part of the ever-important Design Infrastructure Marketing Division of TSMC, which includes the internal and external cloud efforts. TSMC first announced their external cloud offering last year: TSMC announces initial availability of Design-in-the-Cloud via OIP VDE and OIP Ecosystem Partners and has made follow-up announcements with all of the key vendors and participated in multiple cloud panels last week in Las Vegas. Make no mistake, TSMC is a semiconductor cloud pioneer, absolutely.

There are however a couple of things I would like to point out as an objective semiconductor cloud insider. I first heard of TSMC seriously considering the cloud more than 10 years ago. Back then the big hurdle was customer security and having been through TSMC’s security protocol for EDA and IP vendors many times I can tell you TSMC is all about security. But TSMC is also all about enabling customers of all types and getting high quality wafers to the masses and today that means cloud.

Another interesting point in the semiconductor cloud transformation is that systems companies are driving the leading edge foundry business instead of traditional fabless chip companies. Some of these systems companies are actually cloud based companies (Google, Microsoft, Amazon, and Facebook) so there is no security concern there. In fact, cloud security is above and beyond anything we have ever seen in the semiconductor industry and TSMC knows this by direct experience with their cloud customers.

As more systems companies use the cloud for chip design the fabless companies have no choice but to follow. The cloud company chip designers are the extreme case. They can do simulations and verification in hours versus days or weeks. Imagine being able to run a SPICE simulation or characterization run in an hour versus over night?

As I mentioned before, investment in fabless chip companies more than tripled in 2017 and doubled again in 2018. Similar to the fabless transformation, where semiconductor companies no longer had to build fabs, today’s fabless companies don’t have to buy computers and tools, they just go to the cloud where TSMC and EDA is already there waiting for them, absolutely.

One of the more interesting cloud events at #56thDAC was the Mentor Calibre Luncheon (FREE FOOD). SemiWiki Blogger Tom Simon sat in front of me and will blog this in more detail so spoiler alert: Willy Chen was on the panel and he talked about TSMC cutting down the DRC runtime of an N5 testchip from 24 hours to 4 hours using Azure Cloud.  AMD was on the panel and they talked about doing the same thing with their N7 products scaling to 4000 CPU cores using a Microsoft Azure VM (which is an AMD EPYC based server).

Admittedly the AMD presentation was a little self-serving but my takeaway was that AMD partnering with TSMC and pivoting to the cloud for chip design before their much bigger competitors do is a VERY big deal.

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#56DAC – What’s New with Custom Design Platform

#56DAC – What’s New with Custom Design Platform
by Daniel Payne on 06-12-2019 at 10:00 am
Categories: Events, Synopsys, TSMC

Dave Reed, Synopsys

TSMC attends DAC every year and they do something very savvy, it’s a theatre where they invite all of their EDA and IP partners to present something of interest, followed by a drawing for a prize. At the end of the day they even have a nice prize, like a MacBook Air, which I didn’t win. On Wednesday I watched Dave Reed of Synopsys present an update on the Custom Design Platform.

Dave Reed, Synopsys

Tools in the Custom Design Platform include:

Back in April they announced that these tools were certified by TSMC for the 5nm FinFET process node, which is always a big deal for IC design teams pushing the bleeding edge because you need your EDA tools ready.

The integration between these tools is tight, so the phrase used is DRC Fusion or Extraction Fusion, because users don’t want to wait hours streaming data out of one tool and made compatible with the next tool in the flow. Adoption of the Custom Compiler tool increased this past year, now with 100 logos and 3,000 users, and all internal Synopsys IP designs use their own tools.

Analog IC designers know that layout parasitics will affect the performance, accuracy and reliability of their circuits, so the Synopsys flow allows for early use of parasitic estimates, followed by partial extraction and fully extracted netlists.

Each new, smaller process node has an increase in circuit simulations and increase in parasitics, so FineSim can be used to simulate circuits like SERDES, PLL and ADC, now about 3X faster than before. Plus, they’ve added RF simulation to FineSim, so you have another choice than HSPICE.

Automating the layout of analog design is a noble quest, tried by many vendors in the past, so Synopsys continues with a template-based approach where expert layout designers capture their best practices, allowing for transistor size changes. All this is done without having to write code, or becoming a computer science major. I asked Dave about the CiraNova technology that they acquired years ago, and it’s still be used under the hood for layout automation.

IC designers used to work in either a digital or an analog environment, with tedious file interchanges between them, but not any more because Synopsys allows seamless use between the digital flow of IC Compiler II and the analog flow of Custom Compiler. DRC checking can be done either in batch mode or even interactively, saving you time.

Summary

If the Custom Design Platform can be used internally at Synopsys for creating all of their own IP in TSMC nodes at 28nm all the way down to 5nm, then it’s going to work for your project too. This is a competitive market segment and Synopsys keeps plugging away, year by year, making it easier to reach design closure through clever automation.

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