TSMC – Page 14 – SemiWiki

November 1, 2020November 2, 2020

Are TSMC and Intel Partnering in Arizona?

Are TSMC and Intel Partnering in Arizona?
by Daniel Nenni on 11-01-2020 at 10:00 am
Categories: Foundries, Intel Foundry, TSMC
2 Comments

After months of back and forth TSMC finally announced plans to build a fab in Arizona. The announcement was not made in the press or on the most recent investor call but on LinkedIn. A sign of the times I guess but since they need to hire a bunch of semiconductor people it was more than appropriate.

“We’re delighted to catch up with you that TSMC had announced its intention to build and operate an advanced semiconductor fab in Arizona. This U.S. advanced foundry fab not only enables us to better support our customers and partners, we also wish to attract global talents to work with us to change the world.At TSMC, we are working consistently to provide the most advanced technologies to enrich human life. Join us to initiate and witness the new semiconductor era with remarkable people around the world. https://lnkd.in/gX-aEre”

The question is why? TSMC can build fabs in partnership with the Taiwanese Government for pennies on the dollar which is in fact one of the reasons why TSMC is the dominant semiconductor foundry. TSMC did build a leading edge fab in China to better relations with the Chinese Government but spying was a serious problem so TSMC has slowed that effort and now has extensive security protocols in place which is for the greater good of TSMC, absolutely.

One rumor is that TSMC is working with the Federal and State Government to better secure the semiconductor supply chain in the United States. The US Government is finally putting up some money to offset costs of semiconductor manufacturing in the US. Let’s not forget that manufacturing started here but was shooed away by the EPA about the time I started in semiconductors in the 1980s.

U.S. lawmakers propose $22.8 billion in aid to semiconductor industry

Another rumor, which I may have just started, is that TSMC and Intel are already working together in Arizona. Arizona is Intel’s home court so is it a coincidence that TSMC is landing there? Another coincidence, Intel is discussing outsourcing designs to a foundry, a decision to be made by the end of the year according to Intel CEO Bob Swan. I’m sorry but I really don’t believe in coincidence especially when it comes to TSMC. TSMC management is the best this industry has seen in decades so this storyline is all about TSMC.

Another rumor is that Samsung is in the running for the Intel outsourcing gig which was fortified by an Intel executive giving a keynote at the Samsung Foundry day last week. Or maybe that was just part of what Bob Swan said about Intel working closer with the semiconductor ecosystem? Personally I think it was a bad move by Intel to keep TSMC on its toes in the outsourcing discussions. Given AMD’s recent moves, TSMC holds all of the outsourcing cards so Intel should keep this negotiation at the utmost professional level, my opinion.

This reminds me of the head-to-head foundry battle between Altera and Xilinx. In the FPGA business the first to silicon got a market share boost. Altera was partnered with TSMC and Xilinx UMC. Xilinx actually had a dedicated floor in the UMC Hsinchu HQ. At 40nm UMC fell behind so Xilinx jumped to TSMC and actually beat Altera to 28nm. The rest is history but Xilinx beat Altera to first silicon from that day forward and now dominates the $5B+ FPGA market. AMD acquiring Xilinx makes this even more interesting. I will write more about that later because it is a great move by AMD.

Bottom line: To better compete with AMD, Intel will have to closely partner with TSMC like Xilinx did. Just my opinion of course but who would know better than me?

October 23, 2020October 26, 2020

Intel TSMC Update!

Intel TSMC Update!
by Daniel Nenni on 10-23-2020 at 10:00 am
Categories: Foundries, Intel Foundry, TSMC
15 Comments

Based on the Intel investor call yesterday here are some interesting comments Bob Swan made related to Intel outsourcing manufacturing and 7nm progress. Let’s start with the prepared statement:

Bob Swan: “Over the last couple of years, we have been focused on three critical priorities; improving our execution to strengthen our core business, extending our reach to accelerate the growth of the company, and continuing to thoughtfully deploy your capital.

We have and do get great benefits from internal manufacturing. We call it our IDM advantage, because it provides us attractive economics, co-optimization of design and process technology development and supply assurance. So as we engage the ecosystem more broadly, we want to preserve some of the advantages of IDM like schedule, performance and supply, as we work with our strategic partners.

Finally, I want to reiterate our intention to continue investing in leading process technology development to bring future process nodes and advanced packaging capabilities to market. This is a powerful force in creating future differentiation for our products and provides tremendous option value for our business.”

Me: Clearly Bob has been getting grief about his previous comments on outsourcing to pure-play foundries. There has also been speculation about Intel outsourcing to both TSMC and Samsung which fanned the “Intel will go fabless” flames even further.

As I previously stated in Three Things You Have Wrong About Intel: “The one thing Bob Swan will NOT do however is erase the Intel manufacturing legacy and go fabless. Nobody wants that on their semiconductor CEO resume.”

I also find zero truth in the rumor that Intel will use both TSMC and Samsung. To be successful in outsourcing and competing with AMD on a level playing field Intel needs to be exclusive with TSMC. If you outsource to both TSMC and Samsung you will be on the outside looking in, absolutely.

During the Q&A:

“Can you explain how easy it is to transition from TSMC back to your internal manufacturing? How comfortable that is? And would that be for existing type of architecture or more like chiplet type of architectures?“

Bob Swan: “Yes. It’s a good question. I mean I gave kind of the criteria around should we under what circumstances go out more of schedule predictability performance and of economics if you will the bookend on that — on those three criteria really around one, the ease of portability of our technologies to go out. And I would say, we feel very confident in the ability of us being able to port to TSMC.

And the other bookend is in the event that we go out what’s the ease in which we can port back if we conclude that’s the best alternative for either core products or chiplets. I would just say that we feel increasingly confident that yes in fact, if we conclude going out makes sense that we can. And also that in the event we want to port back in, we can as well. And that’s — those are general observations around the bookend questions.”

Me: Hopefully this is based on Bob’s semiconductor terminology naivety. If Intel does in fact “port” designs over to TSMC they will be less competitive than AMD’s direct designs to TSMC in regards to power, performance, and area. Let’s not forget what happened when Apple ported the A9 from Samsung 14nm to TSMC 16nm (ChipGate). It is progress however for Bob to acknowledge they are in fact working with TSMC.

Quick 7nm Update:

Bob Swan: “I would say since the last time we spoke, our 7-nanometer process is doing very well. I mean, last time we spoke we had identified an excursion. We had root caused it. We thought we knew the fix. Now, we’ve deployed the fix and made wonderful progress. But nonetheless, we’re still going to evaluate third-party foundry versus our foundry across those three criteria. And the call will be towards the end of this year early next year.“

Me: I know that Intel has TSMC PDKs but I have not confirmed any tape-outs as of yet. I do think that Intel will outsource price and power sensitive chips to TSMC to better compete in those markets and to reduce manufacturing expenses. Today Intel has three fabs running 10nm chips. If they do partner with TSMC Intel will only need one 7nm fab which is a very attractive CAPEX reduction (fablite versus fabless) while preserving their IDM status.

October 16, 2020October 25, 2020

TSMC Sets the Stage for a Great 2021!

TSMC Sets the Stage for a Great 2021!
by Daniel Nenni on 10-16-2020 at 10:00 am
Categories: FinFET, Foundries, TSMC
5 Comments

TSMC is the bellwether for not just the semiconductor industry but the worldwide economy. TSMC makes semiconductors, semiconductors are where electronics begin and electronics are the foundation of modern life, absolutely.

Apple is also a key economic indicator and as we all know Apple is a strategic partner of TSMC. The Apple TSMC relationship started with the iPhone 6 and other iProducts (20nm in 2014) and continues to this day. The recently introduced iPhone 12 is based on TSMC 5nm. Next year Apple will use an enhanced version of 5nm and in 2022 it will be 3nm.

TSMC raised its 2020 revenue forecast for a second time this year (10% -> 20% -> 30%) with strong demand for 5G and high-performance computing (HPC). The pandemic has resulted in a much stronger emphasis on mobile and cloud computing which should continue in Q4. IoT is also up but Automotive and DCE is down, again due largely to the pandemic. TSMC’s HPC (cloud) content will also benefit from additional AMD and Intel wafer agreements from 7nm down to 3nm over the next five years.

TSMC Revenue Analysis:

In my opinion AI and the cloud will be the key semiconductor drivers moving forward. Vast amounts of data is being generated by our electronic devices. The data is now moving to the cloud for harvesting and monetization. Cars are an easy example. I can assure you that Tesla will be using data from their cars to make more money than from the selling the cars. Think Google and search, Facebook and personal information, or Amazon and shopping, it is all about the data.

It’s interesting to note the process node breakout:
38% of revenue is from mature CMOS nodes. Those nodes were cloned by UMC, SMIC, and GLOBALFOUNDRIES so there is strong competition where designs can be moved from one fab to another with relative ease. That is not the case with FinFET based designs so TSMC’s strong market position will continue to evolve in the future.

For 20nm and 10nm Apple was the only customer to hit HVM thus the shrinkage. TSMC moved 20nm fabs to 16nm and 12nm. The 10nm fabs were moved to 7nm and 6nm. Let’s call it the yield learning two-step where TSMC takes smaller process steps each year versus the much larger traditional semiconductor process steps. For example, TSMC started EUV with a mature 7nm node then went full EUV at 5nm. Intel on the other hand is expected to go from zero EUV at 10nm to full EUV at 7nm.

Notable C. C. Wei quotes from the Q3 2020 Earnings Call:
“For TSMC, our technology leadership position enabled us to capture the industry megatrend of 5G and HPC. We expect to outperform the foundry revenue growth and grow by about 30% in 2020 in U.S. dollar terms.”

“This is pretty hard for me to answer, because I cannot release all the information I got from my customer. But let me say that, on the average, the 5G phone have about 30% to 40% more silicon content as compared with 4G.”

“We are complying full year with the regulations and so and we also notice that there is report saying that the TSMC got the (Huawei) license. We are not going to comment on this unfounded speculation. And we also don’t want to comment on our status right now. For the 4Q shipment to Huawei, the ban, the regulation already say that after September 17th, zero.”

“Certainly TSMC is working with all the customers and view them as our partners. And so we don’t using this opportunity to raise our 8″ wafer price.”

“We are engaging with more customer at N3 as compared with the N5 and N7 at the similar stage. So there’s a lot of customers are working with us. And now, which one in the second half of 2022, which one would be the first product? Actually in smartphone and HPC applications, both.”

Bottom Line: TSMC and the rest of the semiconductor ecosystem seems to be somewhat COVID resistant. The new “work and learn from home” life style is accelerating the digital transformation and that means more semiconductors now and in the future.

About TSMC
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s largest dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

TSMC deployed 272 distinct process technologies, and manufactured 10,761 products for 499 customers in 2019 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 5-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan. For more information please visit https://www.tsmc.com.

October 15, 2020April 27, 2022

ASML is Strong Because TSMC is Hot!

ASML is Strong Because TSMC is Hot!
by Robert Maire on 10-15-2020 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services, TSMC
4 Comments

ASML has strong quarter lead by great Taiwan and EUV
EUV “crossed over” DUV as revenue leader- signaling new era
Taiwan doubles, China grows, Korea weaker, US further behind

ASML hits great numbers
ASML reported revenues of Euro 4B, with income of Euro 2.54EPS, both beating estimates handily. Ten EUV systems were shipped but 14 were recognized. Outlook is for revenues between Euro 3.6B-3.8B, which suggests upside to Euro 4B or better.

Shifting Numbers
There were significant shifts quarter over quarter. EUV went from 7 systems to 14 systems in Q3. Taiwan went from 21% of business to 47% with China going from 23% to 21% of business but increasing in absolute revenues. Korea slumped from 38% to 28% as EUV (which is not memory driven) dominated. The US (read that as Intel) fell off sharply fro.m 17% to 5%.

Intel “crushed” by TSMC in EUV spend- a very bad leading indicator
In the quarter Taiwan (primarily TSMC) was 47% of ASML’s business while the US (primarily Intel) was a paltry 5%. This means that TSMC is spending more or less ten times what Intel is spending on EUV.

In case there was any question as to who is winning Moore’s law by a tidal wave of investments. Intel investors should be scared…very scared. Intel is clearly voting with their feet and matching their words about outsourcing their future to TSMC, who is running away in the Moore’s law race. China spending four times what the US is spending (though none of it on EUV per the embargo) shows that China is deeply building out a strong semiconductor infrastructure and also clearly outspending the US.

Logic dominates at 79% versus memory of 21%
Logic at 79% is one of the highest percentages of revenues we have ever seen and is indicative of memory spending being subdued and perhaps weaker. The fact that this is so weighted to TSMC suggests that they are expecting a lot of business and also expect to put their foot on the EUV accelerator and leave both Intel and Samsung in their EUV dust. Memory obviously does not currently use EUV so the EUV domination of the current quarter will also outweigh memory DUV spend as ArF sales were down sharply.

Some “pushouts” and timing issues in the future?
A while ago we had talked about TSMC slowing spending and the pushouts and timing issues discussed on ASML’s call are likely related to what we heard as we may see some digestion in 2021 after its gigantic spending binge in 2020 (not unlike Samsung’s spending binge of a couple of years ago…).

This talk of pushouts and timing may spook investors but fits the pattern of our suggestion that the COVID led technology, work from home, spending spree will slow as the economic impact of COVID finally trickles down to the semiconductor industry.

Expect a lumpier business going forward
Given the dominance of EUV with systems north of $100M, a few systems more or less can make the quarters lumpier. Customer timing, pushouts and node changes will all add to lumpiness. The reality is that the end game of EUV and High NA remains the same and remains very good. The road to EUV itself was obviously very lumpy with fits and starts so investors should understand this. We would try to take a longer term view, though that may be difficult, and look at longer term trends.

Not much talk about “High NA”
We think that now that EUV is commonplace, the next upside wave will be High NA which will likely be easier (on a relative basis) as compared to the original EUV roll out. We think the potential technology benefits as well as financial benefits may make High NA more attractive than the EUV model. But High NA is still a few years away…..

Crossover from DUV to EUV – passing of the baton
ASML has now officially crossed over from being a DUV dominated company to an EUV dominated company. This brings a different set of challenges but a welcome set.

The key here is that they are the only EUV game in town so it cements their market share at virtually 100% versus having to compete (somewhat) at DUV. This makes the quite unique and valuable as compared to other semiconductor equipment companies who still slug it out in hand to hand battles. ASML is now “above the fray”

The Stocks
We don’t expect much movement on ASML’s stock price as it was already priced for the perfection we got. The talk of pushouts and timing may dampen sentiment and weigh on the stock and offset the positives. We do think it was prudent for management to keep expectations under control. At just over $400 per share ASML is not cheap nor expensive but appropriate given circumstances.

Collateral Stock Impact
In general we think that ASML’s strong performance first out in the quarter bodes well for the semiconductor equipment industry. Our main concern is that the stocks remain ahead of reality. The weak memory showing could be interpreted as bad for memory centric players, most notably Lam (though we have heard they are doing just fine) EUV spend clearly helps KLA and to a slightly lesser extent Applied.

Robert Maire

Also Read:

LRCX weak miss results and guide Supply chain worse than expected and longer to fix

Chip Enabler and Bottleneck ASML

DUV, EUV now PUV Next gen Litho and Materials Shortages worsen supply chain

October 9, 2020October 13, 2020

Three Things You Have Wrong About Intel!

Three Things You Have Wrong About Intel!
by Daniel Nenni on 10-09-2020 at 10:00 am
Categories: Foundries, Intel Foundry, TSMC
17 Comments

First let me tell you that I have nothing but respect for Intel. I grew up with them in Silicon Valley and have experienced firsthand their brilliance and the many contributions they have made to the semiconductor industry. In fact, I can easily say the semiconductor ecosystem would not be what it is today without Intel.

But no company is perfect and there have been many bumps and bruises along their 50+ year journey. The following is just my Intel opinion of course but I will put my semiconductor experience against anyone else in the mainstream media without hesitation.

1. Intel will go fabless

It all started with a story leaked a while back that Intel signed a big wafer deal with TSMC. Next Intel CEO Bob Swan said on a conference call that Intel was in fact looking at outsourcing and the media’s imagination went crazy after that.

Intel insight: CEO on U.S. manufacturing’s role in driving the digital revolution

To be clear, Intel has been a happy TSMC wafer customer for many years so that was not really news. Most, if not all, of it was the result of Intel acquisitions but the point is there has been a trusted Intel/TSMC relationship in place for a long time.

Intel is a semiconductor legend and manufacturing is in their DNA. Whoever says Intel will become fabless (like AMD did) clearly does not work inside the semiconductor industry. It is NOT going to happen.

Here is my professional Intel CEO assessment but first it is important to understand the first 30 years of Intel leadership. Intel was led by some of the top technical CEOs the semiconductor industry will ever see:

Robert N. Noyce
Intel CEO, 1968-1975, Co-founder of Fairchild Semiconductor
Education: Ph.D in physics, Massachusetts Institute of Technology

Gordon E. Moore
Intel CEO, 1975-1987, Co-founder of Fairchild Semiconductor
Education: Ph.D in chemistry and physics, California Institute of Technology

Andrew S. Grove
Intel CEO, 1987-1998, previously worked at Fairchild Semiconductor
Education: Ph.D. in chemical engineering, University of California-Berkeley

Craig R. Barrett
Intel CEO, 1998-2005, Joined Intel in 1974, chairman from 2005 until 2009.
Education: Ph.D. in materials science, Stanford University

The first 30 years of Intel can best be described by Andy Grove’s famous quote “Only the Paranoid Survive” which resulted in Intel being the most dominant semiconductor company in the world. Unfortunately, the next two Intel CEOs were NOT paranoid technical leaders which brought Intel to where it is today, NOT the most dominant semiconductor company in the world.

The current CEO is not a technical leader but he is a financial one and he did not grow up Intel. There is no Intel born swagger in Bob Swan. This is Bob’s big adventure to make his CEO bones in the business world and he will do whatever it takes to be successful as defined by Wall Street, not Moore’s Law. The one thing Bob Swan will NOT do however is erase the Intel manufacturing legacy and go fabless. Nobody wants that on their semiconductor CEO resume.

Intel Fab 42 in AZ now ready to pump out leading edge products

However, I do believe Bob will outsource Intel designed products to TSMC but only for the price and power competitive markets.

Partnering with TSMC will put Intel on a level manufacturing playing field with competitors and Intel will have much higher volumes so margins will be an advantage. Intel can then better focus their internal manufacturing efforts on HPC chips for the cloud which is where the majority of profits will come from over the next 10 years.

2. Intel will take TSMC wafers from AMD

You should also know that the chances of Intel buying up ALL of the TSMC wafers at a given node so AMD can’t have any is ZERO. Yet another dumb thing non semiconductor professionals are saying. Wafer agreements are put in place well in advance of the design start much less manufacturing. TSMC builds fabs based on wafer agreements so there are no capacity surprises, just ask Apple.

To be clear, it takes Intel and AMD longer to design a chip that it does for TSMC to build a fab, do the math.

3. AMD is beating Intel

That is a matter of debate of course. The company financials state otherwise but remember Intel has not had to look in their competitive rearview mirror at AMD since the AM386 more than 30 years ago. Clearly that is no longer the case, I can assure you AMD is in Intel’s competitive cross hairs moving forward. Thus the expanded outsourcing to TSMC, that is a clear shot at AMD. AMD acquiring Xilinx is a clear shot at Intel and Nvidia acquiring Mellanox and Arm is a clear shot at both AMD and Intel.

Bottom line: Competition is the life blood of the semiconductor industry so this is all great news for the ecosystem and the rest of the world, absolutely.

Thus far Bob Swan seems to have the right amount of paranoia to pivot Intel back into a dominant position so two thumbs up for Bob.

On a side note, in 2013 I strongly suggested privately and publicly that Intel should acquire Nvidia and make Jensen Haung Intel CEO number six. That would have been one hell of a ride! Instead Intel hired Brian M. Krzanich which is probably the biggest Semiconductor CEO dumpster fire on record.

October 5, 2020October 20, 2020

Will the U.S. and China go to War for TSMC?

Will the U.S. and China go to War for TSMC?
by Daniel Nenni on 10-05-2020 at 4:00 am
Categories: China, Foundries, TSMC
31 Comments

The semiconductor industry has never been more exciting than it is today and that is a mouthful given what we have accomplished over the last 50 years. From mainframe computers to a supercomputer in our pockets or on our wrists. Even if you don’t believe in miracles, semiconductor technology comes really close, absolutely.

U.S. tightens exports to China’s chipmaker SMIC, citing risk of military use REUTERS

When I started my career 36 years ago you would be hard pressed to find a person who had heard of a semiconductor much less knew what one really was. Today, it is still hard to find people who really know semiconductor design and manufacture (especially in the media) even though you can read about it every day, especially now that semiconductors could lead to the next world war.

Before you write me off as another click-baiting-chicken-little think about how important semiconductors are to modern life. Not just important, semiconductors are critical to modern life. Not just critical, semiconductors could mean the difference between life and death.

Disagree? Imagine our world without electronic devices. Imagine a business or hospital without digital equipment. Imagine a military without high tech gear. Are you getting the picture? Life or death.

Now understand that semiconductors are where modern electronics begin and end for that matter. Also understand that the semiconductor chip may have been invented in the United States but today it is a worldwide supply chain.

To be clear, no one country can succeed in semiconductor design and manufacture without others. Having grown up in Silicon Valley and spending the majority of my semiconductor professional life traveling the world I know this firsthand, front row seat, I lived it.

Being from a military family and a military history enthusiast I also know a little bit about war. My grandfather served in WWI as an Army medic and lived to tell about. In fact, he lived 102 years under my care so I heard all about it. My other Grandfather was at Pearl Harbor, my father served in Korea, and my Uncle in Vietnam. War is hell.

One of the strategic things to do when waging a war is to cut off their supply lines, right? Food, water, fuel, raw materials, etc… You can now add semiconductors to that supply list.

So why is the United States today cutting off the semiconductor supply line to China? It’s an act of war and if there is an actual war over semiconductors, where will it be fought?

Taiwan of course. Taiwan is the semiconductor manufacturing hub of the world. Taiwan is also the Republic of China, which is what my passport says, and even without semiconductors China wants political control over Taiwan. Something like what is happening in Hong Kong only with a full-on war declared.

Why is Taiwan so important to the semiconductor supply chain? Because Taiwan is the home of TSMC (Taiwan Semiconductor Corporation), the worldwide champion of semiconductor manufacturing. My first book “Fabless: The Transformation of the Semiconductor Industry” goes into more detail on how TSMC came about but the bottom line is; It’s all about the ecosystem (supply chain). Hundreds of companies around the world brought us to where we are today and nothing short of a war can stop the semiconductor ecosystem from succeeding.

Could it even be possible? China at war with the US through Taiwan? Ten years ago from the Lobby of Hotel Royal in Hsinchu I would have said absolutely not. Today, sheltering in Silicon Valley, given the current political instability and oncoming economic challenges, given the eye-for-an-eye +1 behavior of the US and China leadership, I say war is probable. Unless of course the world recognizes semiconductors as a matter of life or death and gets civilized around it. Just my semiconductor professional opinion of course.

October 4, 2020October 6, 2020

5G, Hyperscaling and the Resurgence of Consumer Silicon

5G, Hyperscaling and the Resurgence of Consumer Silicon
by Ramsay Allen on 10-04-2020 at 6:00 am
Categories: 5G, IP, Moortec, TSMC

At the recent TSMC OIP Ecosystem Forum and Technology virtual events, TSMC re-affirmed their previous prediction that 5G is going to be a multi-year silicon mega-trend with the biggest drivers being the ramp up of 5G handsets, supporting infrastructure and the continued growth of high performance computing (HPC).

We all want the luxury of live streaming, whether it be a concert or sports event, playing the latest games or watching HD movies on our phone, but what is it that actually allows 5G ASIC designers to deliver this enhanced level of user experience? Today’s Semiconductor advanced node technology really is the beating heart of 5G network technology. Powering network base stations, cars, smartphones, and other connected devices, but 5G also plays an integral part of a much bigger technology phenomenon…Hyperscaling.

5G infrastructure is extremely power hungry and generally requires ~3 times the number of base stations compared to older technologies such as LTE, due to the higher frequencies involved. Moortec is already working with customers in the 5G space to help address some of these infrastructure power issues.

5G Silicon Challenges

5G enabled devices such as handsets, tablets and wearables have certainly helped revitalize the consumer electronics space as they have moved from typically planar nodes down to FinFET process technologies like 5nm.

This step change does however present designers with specific challenges, one of the biggest being increased thermal activity associated with the data intensive workloads associated with the system. Battery life can also be an issue when running 5G and associated applications like video, and gaming etc. If the thermal conditions are not carefully monitored and controlled, handsets may either switch to a lower power 4G mode or even turn off altogether. As a user why do I care? Well, apart from the handset becoming noticeably warmer to the touch, your video download will take longer or freeze and your phone will need recharging more frequently as the battery will drain faster.

A 5G small cell can be operational for over a decade in potentially hostile environments, without any forced air cooling and as such it is particularly important to be able monitor them remotely in the field.

Moore’s Law

In the last instalment of the Moortec ‘Talking Sense’ blog my colleague Tim Penhale-Jones talked about the impact that Moore’s law and Dennard Scaling have had on the advanced node semiconductor sector. For some time, we have been cramming ever increasing amounts of processing power into each 1mm² of silicon and this has enabled the 5G technology that we see emerging today. However, the pressure continues to Miniaturize (device size), Maximise (power & performance) and Optimize (reliability & battery life) and in order to continue to do this successfully it is critically important to understand the dynamic conditions within the device itself.

Benefits of In-Chip Monitoring for 5G Devices

By implementing highly configurable, real time embedded sensing fabrics, chip designers can address some of the challenges associated with overheating, reduced data throughput and diminished battery life. This enhances the overall user experience in consumer products like 5G handsets and increases the performance optimization and reliability of infrastructure devices in the field.

To find out how Moortec’s in-chip monitoring technologies and sensing fabrics could benefit your next advanced node 5G project contact us today.

In case you missed any of Moortec’s previous “Talking Sense” blogs, you can catch up HERE.

September 25, 2020July 18, 2025

Synopsys talks about their DesignWare USB4 PHY at TSMC’s OIP

Synopsys talks about their DesignWare USB4 PHY at TSMC’s OIP
by Tom Simon on 09-25-2020 at 6:00 am
Categories: Events, Foundries, IP, Synopsys, TSMC
2 Comments

When USB initially came out it revolutionized how peripherals connect to host systems. We all remember when Apple did away with many separate connections for mouse, keyboard, audio and more with their first computers supporting USB. USB has continued to develop more flexibility and more throughput. In 2015 Apple again introduced the MacBook with just a single USB Type C connector and only a headphone jack. The Type C connector has been used for USB 3.2, but will now also be used for the latest USB specification – USB4. Synopsys recently gave an excellent presentation on USB4 and their DesignWare USB4 PHY IP at The TSMC OIP event. Despite all the changes and improvements in USB, each generation maintains compatibility with earlier versions. Gervais Fong, Director of Marketing at Synopsys, clearly described how backwards compatibility is maintained while impressive new features and performance are added.

In 1998 the first specification for USB 1.1 allowed data transfers of 1.5 or 12 Mbits/s. Leaping forward, USB4 supports all previous data rates and can run at 40 Gbits/s max aggregate bandwidth. One of the biggest additions are the USB4 host controller and device routers. Nevertheless, USB4 maintains bypasses for 1 and 2 lane legacy USB up to 20Gbits/s and 1, 2 or 4 lanes for DisplayPort 1.4 TX up to 20 Gbits/s. This permits older devices that do not use a USB router to still transfer data. USB4 also supports tunneling of PCIe, USB and DisplayPort at up to 40 Gbits/s. USB4 incorporates UMTI+ and PIPE5.

Gervais included a useful slide showing USB4’s five different operating modes. Rather than try to describe the five modes, the slide is included below. The trend of combining protocols is significant. It means that with a single connector high speed data for peripherals, networking, storage and displays are all supported. This improves the user experience and offers unmatched flexibility. A high level of interoperability is available because Apple and Intel are both contributing and supporting USB’s evolution.

Five Modes for DesignWare USB4 PHY

While the user experience is improving, chip designers who want to incorporate USB4 need to ensure that their USB silicon is fully compliant and has been completely verified. The USB4 PHY alone needs to support a dizzying array of operating modes, configurations, protocols and speeds. Gervais points out the USB4 PHY is not just handling USB, it is handing DisplayPort and Thunderbolt as well. The PHY has to interface with and be compatible with the router and controllers.

Synopsys has developed a DesignWare USB4 PHY that meets all of the specification’s requirement and is available on 12nm, 6/7nm and 5nm. It is built on an optimized, low power SerDes. Gervais said that they have over 100,000 CPU hours of simulation with Synopsys routers and controllers.

Gervais also talked about their test silicon from TSMC N5 that is now being tested. The PHY includes a programmable 3-tap Feed Forward Equalizer that is used to adjust the equalization for the various operating modes and frequencies. This is essential for meeting the USB4 PHY specifications. They have achieved first silicon success in TSMC N5P. The eye diagram for this silicon at 20 Gbits/s shows a wide open eye for TX. The receive path includes a Continuous Time Linear Equalizer and 1-tap Decision Feedback Equalizer with programmable settings.

The complete DesignWare USB4 solution from Synopsys includes PHYs, router, controller, verification IP and supporting subsystems. The talk presented a comprehensive overview of USB4 and its requirements, as well as an insightful look at the Synopsys DesignWare that supports interface development.

Also Read:

AI/ML SoCs Get a Boost from Synopsys IP on TSMC’s 7nm and 5nm

Parallel-Based PHY IP for Die-to-Die Connectivity

Making Full Memory IP Robust During Design

September 9, 2020September 9, 2020

Highlights of the TSMC Technology Symposium – Part 3

Highlights of the TSMC Technology Symposium – Part 3
by Tom Dillinger on 09-09-2020 at 8:00 am
Categories: Events, Foundries, TSMC

Recently, TSMC held their 26th annual Technology Symposium, which was conducted virtually for the first time. This article is the last of three that attempts to summarize the highlights of the presentations. This article focuses on the technology design enablement roadmap, as described by Cliff Hou, SVP, R&D.

Key Takeaways

Design enablement is available for N7, N6, N5, and N3, both EDA reference flows and Foundation IP.
N3 “specialty” IP is in development, in collaboration with the IP Partners.
Automotive (AEC-Q100) Grade 1 qualification is progressing for N7, offering an attractive PPA migration from N16 (available 4Q20).
EDA tool support is available for leading 2.5D/3D package technologies: SoIC, InFO, CoWoS. New EDA flow support required for (>1X reticle size) packages will be available 4Q20 (e.g., package warpage analysis).

Introduction

It is no secret that a major factor in TSMC’s foundry success has been the investment in the design enablement ecosystem, which spans the collaboration between TSMC and:

EDA partners

enhancing tool algorithms for new process node requirements, from place-and-route to physical design layout verification
collaborating with TSMC on implementation of trailblazing designs, from process bring-up memory array testsites to advanced Arm cores
preparing an integrated (and qualified) “reference flow” for a new process node

IP providers

developing critical IP functionality in a new node to complement TSMC’s Foundation IP
qualifying test silicon in the new node for the various TSMC platforms – IoT, mobile, HPC, and (the most demanding) automotive

Design Center Alliance (DCA) service providers

offering a range of front-end design resources, back-end implementation skills, custom design support, and DFT services

Value Chain Aggregator (VCA) providers

offering a broad range of support, throughout the IC “value chain”, extending all the way from product architecture definition to final wafer assembly/test/qualification services

and, the most recent addition to the Open Innovation Platform (OIP) ecosystem,

Cloud Alliance partners

collaborates with TSMC and EDA partners to provide a secure, scalable cloud compute environment for some (i.e., burst demand) or all of the IC design flow

The heart of the Open Innovation Platform is the TSMC Design Enablement (DE) organization. Cliff provided an update on the enablement status for the upcoming advanced process nodes and packaging technologies, across the various design platforms.

Tool Certification

It should be noted that EDA tool certification at a new node is far more complex than simply running a set of SPICE circuit simulations and updating the runsets used for DRC/LVS/ERC physical verification. Each node transition commonly introduces new, complex layout design rules, often requiring significant algorithm development by the EDA partner to provide the functionality and language commands needed to code the runset. Multi-patterning, forbidden pitches, run-length dependent rules, line cut rules, and specific fill requirements across multiple mask levels all have been introduced at recent nodes. For block composition flows at successive nodes, each cell library may have rules that define new constraints on cell placement, pin access routing, and power distribution/gating. Reaching tool/flow production certification is no mean feat.

Additionally, new process nodes (and their application markets) may necessitate the introduction of completely new flows:

an “aging flow” that integrated the effects of NBTI, PBTI, and HCI into a measure of performance degradation over time, using new device aging models
a local heating flow that reflects how the unique thermal dissipation paths in FinFET-based designs impact chip failure mechanisms (especially electromigration)

N7/N6/N5/N3

full EDA tool certification, for both custom IP design and cell-based block composition, for all nodes (N5: v0.9 PDK; N3: v0.1 PDK)
EDA “utility” certification (e.g., fill algorithms)

(Cliff’s certification charts focus on tool offerings from the major EDA Partners.)

N6 is a variant of N7, offering a yield improvement (fewer mask layers) and the ability to achieve a logic block density improvement using an optimized N6 high-density cell library.

N7 automotive platform flows and IP ready (AEC-Q100 Grade 1)
N5 automotive platform in 2022 (Grade 1)

Note that there are two common reliability qualification designations for the AEC-Q100 automotive platform, both based on zero fails after 1K hours HTOL stress test on sampled lots, plus HAST and temperature cycling endurance tests: Grade 1: -40C to 125C; Grade 0: -40C to 150C (for “under the hood” applications).

When describing the (Grade 1) qualification activity for N7 and N5, Cliff highlighted some of the additional design enablement considerations for the automotive platform:

a “low DPPM” Design Rule Manual and DRC runset
aging model qualified for the automotive part lifetime and operating temperature
automotive platform-specific EM rules
automotive platform-specific latchup and ESD design rules
soft error upset analysis

Since the automotive “defect parts per million” shipped criterion is stringent, a specific set of DRC rules at the node is employed.

The demand for high-throughput, low power computation in the vehicles of the future is great , and must also meet the AEC-Q100 qualification criteria (Grade 1). The TSMC design enablement team is extending the technology definition, design rules, models, and Foundation IP evaluation to provide this support at advanced process nodes.

N12e

At the Symposium, TSMC introduced a new ultra low power N12FFC+ variant, denoted as N12e. This process is specifically designed for IoT (and AIoT, or AI at the edge) applications, offering a transition from N22ULL (planar) to N12e (FinFET).

N12e EDA tools certified (major new features added, listed below)

The design enablement for N12e is faced with the challenges of:

analyzing and modeling layout dependent effects (LDE), where device impacts are magnified at low VDD
developing SPICE models valid for VDD=0.4V
providing statistical device model support valid for low VDD operation
providing cell characterization, delay calculation, and static timing analysis support valid for low VDD operation; specific focus is required for flip-flop setup/hold measures at low VDD

(At low supply voltage, the cell delay arc statistical variation is decidedly non-Gaussian, due to the “near Vt” operation.)

Advanced Packaging: SoIC, InFO, CoWoS (3D Fabric)

With the rapid growth of 2.5D and 3D packaging options, the TSMC Design Enablement team has expanded their scope to include the appropriate physical verification and electrical/thermal analysis EDA flow support:

redistribution Layer (RDL) routing and through via routing rules (through CoWoS silicon interposer or InFO wafer compound)
routed interconnect impedance matching and shielding requirement (e.g., on a CoWoS interposer, to support wide bus width connectivity to HBM stacks)
die-to-die bond rules (SoIC)
LVS verification throughout the 2.5D/3D package connectivity
RC and RLC parasitic extraction for a complex package geometry – especially, inter-die coupling capacitance for SoIC
IR and EM analysis of the power distribution network throughout the package assembly
signal integrity analysis
thermal analysis – especially, through 3D stacked die
ESD analysis

EDA tools are ready for SoIC (3D), InFO and CoWoS (both 2.5D), with the following exceptions, as new flows need to be certified:

large (>>1X max reticle size) multi-die floorplan package “warpage analysis” (available for InFO and CoWoS in 4Q20)
static timing analysis for stacked die in an SoIC, with temperature/voltage distribution and “multi-corner” process variation between die (available 4Q20)

The TSMC Design Enablement team continues to provide EDA tool and reference flow support for the challenges introduced by advanced process nodes, ranging from new aging models to timing/electrical analysis at low VDD operation. The 2.5D and 3D package technology offerings require a close collaboration between TSMC and EDA developers to address new requirements – e.g., unique package interconnect/via design rules, stacked die timing analysis.

As mentioned above, TSMC’s focus on design enablement distinguishes their process and package technology offerings.

For more information on the TSMC Design Enablement support for the OIP Partners and platforms, please follow these links – OIP and Technology Platforms.

-chipguy

Highlights of the TSMC Technology Symposium – Part 1

Highlights of the TSMC Technology Symposium – Part 2

September 7, 2020January 21, 2021

Dolphin Design – Delivering High-Performance Audio Processing with TSMC’s 22ULL Process

Dolphin Design – Delivering High-Performance Audio Processing with TSMC’s 22ULL Process
by Mike Gianfagna on 09-07-2020 at 10:00 am
Categories: AI, Dolphin Design, Events, IP, TSMC

TSMC held their very popular Open Innovation Platform event (OIP) on August 25. The event was virtual of course and was packed with great presentations from TSMC’s vast ecosystem. One very interesting and relevant presentation was from Dolphin Design, discussing the delivery of high-performance audio processing using TSMC’s 22ULL process through their computing platforms and subsystems.

The OIP event followed TSMC’s Technology Symposium, which was held the day before. I’ve heard from more than one person that these virtual events were well produced, easy to follow and had the added advantage of not needing to get up at the crack of dawn to get a parking spot and a good seat. Virtual events are clearly the new normal.

Dolphin’s presentation began by discussing the business trends for AI applications in audio markets. This was followed by a discussion of ultra-low power (uLP) audio processing, an application use case and an overview of Dolphin’s platforms for audio processing. I’ll provide some highlights of each section of their presentation here.

Business Trends in AI Audio Markets

This section began by pointing out that voice is the easiest form of a user interface. This includes the following properties:

Intuitive
Quick and accurate
No contact
Straightforward
Easy integration

Voice-enabled devices need to address several technical challenges, including:

Voice detection
Keyword spotting
- Voice pickup & noise reduction
Speaker separation
Active noise control
Speech recognition
Low power

So, voice-enabled devices represent the next revolution for user experience. The opportunity is to provide power optimized, local AI processing for things like speech recognition, wake-word detection and voice detection. Local processing will deliver better latency, lower cost and improved privacy since voice data is not sent to the cloud.

uLP Voice Detection and Keyword Spotting

Dolphin Design provided some very good detail on the benefits of their IP and associated platforms for voice detection. You can also see Tom Simons’s post on Dolphin Design and voice detection here. The figure below illustrates the high-performance and ultra-low power audio processing they can deliver for voice detection.

The Dolphin approach for voice detection provides the following benefits:

Stand-alone IP embedding a smart algorithm to detect voice activity
Automatic tuning of detection algorithms to the level of background noises
Short detection latency to avoid the need of buffering the audio stream
Ambient noise sensing for optimal adaptation of the key word spotting (KWS) algorithm to environmental conditions

A typical record lifetime of systems with a 25 mAh battery is ~5 hours without Dolphin technology and ~38 hours with Dolphin technology.

For keyword spotting, Dolphin Design can also deliver high-performance and ultra-low power audio processing using their MCU subsystem as shown in the figure below.

Using Dolphin’s CHAMELEON MCU subsystem yields the following benefits:

Up to 80x power reduction
Bringing KWS in µW range
No need for accelerator
Enables faster inference
- for multiple speakers
- for beamforming
- still in mW range

Application use case: True Wireless Stereo (TWS) Earbuds

An example application for TWS earbuds was presented. Several Dolphin Design platforms and subsystems were used in this application. The benefits of each of these capabilities can be summarized as follows:

CHAMELEON MCU Subsystem
- Compatible with main MCU
- High bandwidth through low latency interconnect
- Tiny ML accelerator with 32 MAC/cycle
- <20 µA/MHz & 2µA deep sleep in TSMC 22uLL

BAT Audio Platform
- Up to 768 kHz sample rate
- Less than 7us analog to analog latency
- Up to 8 analog and digital mic inputs
- I2S/AHB data interface & I2C/APB control interface

SPIDER Power Management
- Customizable & tailored power network
- Standardized & predictable power management
- 250 nA quiescent DCDC
- 150 nA quiescent LDO

PANTHER DSP
- Up to 64 MAC/cycle
- Up to 16 cores scalability
- Standard AXI interface
- Enhanced SIMD DSP, NN instructions

Dolphin Design Platforms for Audio Processing

The following diagram summarizes Dolphin Design platforms and their capabilities in the field of audio and processing applications.

Dolphin summarized how they are delivering high-performance audio processing with TSMC’s 22ULL processes follows:

Audio/Voice markets will be dominant AI market in coming years
- Smart Sensors approach will be the driving force
Dolphin Design has a long experience in Audio Codecs
New platforms will enable Voice User Interface
- uLP speech recognition for enabling the voice-control world
- Open platform as a design Backbone reusable for multiple projects, multiple processes, multiple processor vendors
- Reduce key expertise bottlenecks
- Faster TTM thanks to ready-to-use audio platform

You can learn more about the platforms and systems available from Dolphin Design here