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TSMC Explains the Fourth Era of Semiconductor – It’s All About Collaboration

TSMC Explains the Fourth Era of Semiconductor – It’s All About Collaboration
by Mike Gianfagna on 08-13-2021 at 6:00 am
Categories: Events, Foundries, TSMC
1 Comment

TSMC Explains the Fourth Era of Semiconductor – Its All About Collaboration

The 32nd VLSI Design/CAD Symposium  just occurred in a virtual setting. The theme of the event this year was “ICs Powering Smart Life Innovation”. There were many excellent presentations across analog & RF, EDA & testing, digital & system, and emerging technology. There were also some excellent keynotes, and this is where I’d like to focus. TSMC’s Suk Lee presented a keynote entitled, “Moore’s Law and the Fourth Era of Semi”.  Anything that attempts to make sense out of the storied and turbulent history of the semiconductor industry catches my attention. As explained by TSMC, the fourth era of semiconductor is all about collaboration. Let’s a take a closer look.

The keynote was presented by Suk Lee, vice president, Design Technology Platform at TSMC. I’ve known Suk for a long time, so this presentation was a must-see for me.  I sold to Suk when I was at Zycad and he was at LSI Logic. That was challenging as Suk is not easily impressed. I then worked with Suk at Cadence where we achieved some great results. His high bar for technical excellence was alive and well and it helped us. Since Cadence, I’ve had a few gigs in companies that were part of the Design Technology Platform Suk oversees at TSMC. Again, meeting his high bar for technical excellence made us all better. Let’s look at the history of the semiconductor industry, according to TSMC and Suk Lee.

The First Era of Semiconductor – IDM

To begin with, the transistor was invented at Bells Labs, followed by the first integrated circuit at Texas Instruments. Things got really interesting when the first monolithic integrated circuit was developed at Fairchild. The photo below, courtesy of the Computer History Museum shows some of the early pioneers involved in this work. You will recognize their names. Note everyone is wearing a jacket and tie. This might be something to think about as you plan your return to the office.

Fairchild pioneers

And so, the first era of semiconductor was born – the Era of the integrated device manufacturer, or IDM. These were monolithic companies that did it all – chip design, design infrastructure, chip implementation and process technology. I started my career in the design infrastructure area at an IDM called RCA. Suk points out that integration and invention went hand-in-hand at IDMs. The opportunity to create something completely new was quite exciting. I know that from first-hand experience. Custom chips were the domain of IDMs. They had all the infrastructure, technology and staff to get it done. And so custom chips were limited to IDMs or companies with enough money to fund the massive development at an IDM. That all changed when we got to the second era of semiconductor.

The Second Era of Semiconductor – ASIC

Companies like LSI Logic and VLSI Technology were the pioneers for this phase. Now, design infrastructure, chip implementation and process technology were provided to all by the ASIC vendor. The semiconductor industry began to disaggregate during this time. Armed with design constraints, a much broader community of engineers could design and build a custom chip. The technology became democratized, and the world was never the same.

The Third Era of Semiconductor – Foundry

The third era is essentially a maturation of the second era. All of the steps in IC design and fabrication are quite challenging. Assembling an ecosystem where each company focuses on their core competence is a great way to manage complexity. This is what happened in the third era. Chip design and implementation were addressed by fabless semiconductor companies, design infrastructure was delivered by EDA companies and process technology was developed and delivered by foundries. TSMC was a key pioneer for this phase.

The Fourth Era of Semiconductor – Open Innovation Platform

Watch carefully, we’re about to come full circle. As the semiconductor industry continued to mature, process complexity and design complexity began to explode. Esoteric and subtle interactions between process technology, EDA, IP and design methodology became quite challenging to coordinate with a disaggregated supply chain. TSMC was the pioneer for this era as well.

The company realized that a substantial amount of coordination and communication was needed between the various parts of the disaggregated ecosystem. A way to bring the various pieces closer together to foster better collaboration was needed. And so, TSMC developed the Open Innovation Platform®, or OIP. They began this work early, when 65 nm was cutting edge. Today, OIP is a robust and vibrant ecosystem.

The infrastructure provided by TSMC paved the way for improved collaboration and coordination, creating a virtual IDM among its members. This provides TSMC’s customers the best of both the monolithic and disaggregated models. It changed the trajectory of the semiconductor industry and provided TSMC with a substantial competitive edge.

There are many benefits of the model. The ability to perform design technology co-optimization (DTCO) is one that is quite useful. The figure below illustrates the breadth of TSMC’s OIP. Advanced semiconductor technology requires a village, a big village.  To help decode some of the acronyms DCA stands for design center alliance and VCA stands for value chain aggregator.

TSMC OIP®

We’ve now reached the end of the semiconductor history lesson, for now. Getting to this point has been quite challenging and exciting. Suk Lee did a great job explaining the history. TSMC made it happen and we’re better as a result. I look forward the next phase of semiconductor growth and where it may take us. For now, remember that the fourth era of semiconductor is all about collaboration.

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TSMC Design Considerations for Gate-All-Around (GAA) Technology

TSMC Design Considerations for Gate-All-Around (GAA) Technology
by Tom Dillinger on 07-12-2021 at 6:00 am
Categories: Events, Foundries, TSMC
4 Comments

mobility differences 3

The annual VLSI Symposium provides unique insights into R&D innovations in both circuits and technology.  Indeed, the papers presented are divided into two main tracks – Circuits and Technology.  In addition, the symposium offers workshops, forums, and short courses, providing a breadth of additional information.

At this year’s symposium, a compelling short course was:  “Advanced Process and Device Technology Toward 2nm-CMOS and Emerging Memory”.  A previous SemiWiki article from Scotten Jones gave an excellent summary of the highlights of (part of) this extensive short course. (link)

Due to space limitations, Scotten wasn’t able to delve too deeply into the upcoming introduction of Gate-All-Around (GAA) technology.  This article provides a bit more info, focusing on material presented in the short course by Jin Cai from TSMC’s R&D group, entitled:  “CMOS Device Technology for the Next Decade”.

FinFET to GAA Transition

Successive generations of FinFET process technology development have resulted in tighter fin pitch and taller fins, with increasingly vertical fin sidewall profile.  Significant improvements in drive current per unit area have been realized.  The electrostatic control of the gate input over the three surfaces of the vertical fin has also improved subthreshold leakage currents.

Yet, Jin highlighted that, “Free carrier mobility in the vertical fin is adversely impacted for very small fin thickness.  TSMC has introduced SiGe (for pFETs) at the N5 node, to improve mobility.  Strain engineering continues to be a crucial aspect of FinFET fabrication, as well.”  (nFET:  tensile strain; pFET:  compressive strain)

The figure below illustrates the trends in short-channel effect and carrier mobility versus fin width.

Jin continued, “An optimal process target is ~40-50nm fin height, ~6nm fin thickness, and ~15nm gate length, or 2.5X the fin thickness.”

The next step in device scaling is the horizontal gate-all-around, or “nanosheet” (NS) configuration.  A superlattice of alternating Si and SiGe layers are fabricated on the wafer substrate.  A unique set of etch/dep steps are used to remove the SiGe material at the NS layer edges and deposit a spacer oxide in the recessed area, leaving the Si layer sidewalls exposed.   Source/drain epitaxy is then grown out from the Si sidewalls, providing both the S/D doping and structural support for the Si nanosheets.  The SiGe layers in the nanosheet stack are then selectively removed, exposing the Si channels.  Subsequent atomic layer deposition (ALD) steps introduce the gate oxide stack, potentially with multiple workfunctions for device Vt offerings.  Another ALD step provides the gate material, fully encapsulating the nanosheet stack.

Jin focused on the carrier mobility characteristics of the nanosheet-based GAA device, as representative of performance.  (More on GAA parasitic capacitance and resistance shortly.)  The figure below provides an illustration of the crystalline orientation for GAA devices, to optimize the lateral mobility in the horizontal nanosheet layer channels.

Jin highlighted a key issue facing the development of NS process technology – the (unoptimized) hole mobility is significantly less than the nFET electron mobility, as illustrated below.

Digression:  Carrier Mobility and Circuit Beta Ratio

When CMOS technology was first introduced, there was a considerable disparity in nFET electron and pFET hole mobility in strong inversion.  A general circuit design target is to provide “balanced” RDLY and FDLY delay (and signal transition) values, especially critical for any circuit in a clock distribution network.  As a result, logic circuits adopted device sizing guidelines, where Wp/Wn was inversely proportional to the carrier mobility ratio – i.e., Wp/Wn ~ mu_electron/mu_hole.  For example, a device sizing “beta ratio” of ~2.5 was commonly used.

(Wp and Wn are “effective” design values – for logic circuit branches with multiple series devices, to maintain the same effective drive strength, wider devices are required.)

With process technology scaling employing thinner channels below the oxide surface, and with extensive channel strain engineering, the ratio between electron and hole mobility was reduced, approaching unity.  Indeed, as illustrated below, the introduction of FinFET devices with quantized width values depended upon the reduction in carrier mobility difference.  (Imagine trying to design logic circuits with a non-integral beta ratio in the 2+2 fin standard cell image shown below.)

Nanosheet Circuit Design

The figure above depicts a standard cell library image, for both current FinFET and upcoming nanosheet technologies.  Unlike the quantized width of each fin (Wfin ~ 2*Hfin + Tfin), the nanosheet device width is a continuous design parameter, and (fortuitously) can more readily accommodate a unique beta ratio.

Note that there will be limits on the maximum nanosheet device width.  The process steps for selectively removing the interleaved SiGe superlattice layers and the deposition of the oxide and gate materials need to result in highly uniform surfaces and dimensions, which will be more difficult for wider nanosheet stacks.

Speaking of nanosheet stacks, it should also be noted that the layout device width is multiplied by the number of nanosheet layers.  Jin presented the results of an insightful analysis evaluating a potential range of layers, as shown below.

A larger number of layers increases the drive current, but the (distributed) contact resistance through the S/D regions to the lower layers mitigates this gain.  The majority of the published research on nanosheet technology has focused on ~3-4 layers, for optimal efficiency.

Parenthetically, there has also been published research investigating nanosheet fabrication process techniques that would locally remove one (or more) nanosheet layers for a specific set of devices, before ALD of the surrounding oxide and gate.  In other words, some devices could incorporate less than 3 layers.  Consider the circuit applications where a weak device strength is optimum, such as a leakage node “keeper” or a pullup device in a 6-transistor SRAM bitcell.  Yet, the resulting uneven surface topography adds to the process complexity – the upcoming introduction of GAA technology may not offer a variable number of nanosheet layers.  The same surface topography issue would apply toward a GAA process that would attempt to build nFETs from superlattice Si layers and pFETs from superlattice SiGe layers, assuming the ability to selectively etch Si from SiGe for pFETs.

The net for designers is that GAA technology will offer (some) variability in device sizing, compared to the quantized nature of FinFETs.  Leakage currents will be reduced, due to the GAA electrostatics surrounding the nanosheet channel (more on that shortly).

Analog circuits may be more readily optimized, rather than strictly relying upon a ratio of the number of fins.  SRAM cell designs are no longer limited to the PD:PU:PG = 2:1:1 or 1:1:1 FinFET sizing restrictions.

Currently, FinFET standard cell libraries offer cells in integral 1X, 2X, 4X drive strength options, often with 3 or 4 device Vt variants.  With greater sizing freedom (and potentially fewer device Vt alternatives) in a GAA technology, library designers have a different set of variables from which to select.  It will be interesting to see how cell library designers utilize this device flexibility.

Ongoing Nanosheet Fabrication R&D

Jin described three areas of active process R&D for more optimum nanosheet characteristics.

  • increased SiGe stoichiometry for pFETs

The lower hole mobility in nanosheet Si layers is a concern.  Research is ongoing to increase the SiGe composition in pFET nanosheet layers (without adopting a SiGe superlattice stack, due to the topography difficulties mentioned above).  One approach would be to “trim” the pFET Si nanosheet thickness after superlattice etch, and deposit a SiGe “cladding” layer, prior to oxide and gate deposition.  The difficulty would be maintaining a uniform nanosheet thickness after the trim and SiGe cladding deposition steps.

  • optimization of parasitic Cgs/Cgd capacitances

FinFETs have a (relatively) high parasitic capacitance between gate and source/drain nodes, due in part to the gate vertical sidewall-to-S/D node capacitance contribution between fins.  The horizontal nanosheet utilizes a different gate-to-S/D oxide orientation, arising from the inner spacer deposited in the SiGe superlattice layers prior to S/D epitaxy and SiGe etch.  Jin highlighted that the nanosheet and recessed oxide dimensions need to be optimized not only for the drive current, but also the parasitic Cgs/Cgd capacitances, as illustrated below.

  • bottom nanosheet “mesa” leakage

The GAA topology improves upon the (3-sided) FinFET electrostatics, reducing subthreshold device leakage current.  However, there is a parasitic leakage path for the very bottom (or “mesa”) nanosheet layer.  After the superlattice etching, oxide dep, and gate dep steps, the gate-to-substrate electrostatics offers a (non-GAA) channel current path.

As illustrated above, Jin highlighted R&D efforts to reduce this leakage current contribution, through either:

  • additional impurity introduction below the nanosheet stack
  • partial dielectric isolation between the substrate and S/D nodes
  • full dielectric isolation between the substrate, S/D nodes, and bottom layer nanosheet gate

Summary

Jin’s presentation offered great insights into the relative characteristics of FinFET and GAA devices, as process nodes evolve to the horizontal nanosheet topology.  Designers will benefit from reduced leakage currents and design sizing flexibility, although disparities between nanosheet channel electron and hole mobility will require renewed consideration of circuit beta ratios.  Ongoing process R&D efforts are seeking to reduced this carrier mobility difference, and optimize parasitic Rs, Rd, Cgs, and Cgd elements.

Jin presented a rough timeline shown below, for the introduction of GAA nanosheet technology, before new device configurations (e.g., 3D silicon fabrication) and non-silicon materials (e.g., 2D semiconductors) will emerge.

As Scotten also suggested in his article, if you have the opportunity, I would encourage you to register and view this enlightening VLSI Symposium short course.

-chipguy

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Apple’s Orphan Silicon

Apple’s Orphan Silicon
by Paul Boldt on 07-11-2021 at 6:00 am
Categories: TSMC
7 Comments

T2 die anno lr

Apple’s recent Spring Loaded Event brought us M1-based iMacs.  After the MacBook Air and 13” MacBook Pro in the fall, iMacs are the third Mac to jettison Intel processors.  With this transition Apple’s T2 chip enters End of Life status, so to speak.  The T2 is a bit of an enigma and now it does not have much time left.

We know it performs a wide range of tasks in Macs, including security, encryption, video processing, storage control and housekeeping.  This 2019 AppleInsider article tested encode times for Macs having the same processor, where one had a T2, and one did not.  The Mac with the T2 executed the encode in 1/2 the time.

Despite all this functionality we know surprising little about the T2.  There simply is not much information floating around.  Wikipedia does not even report a die size or process node.  Did Apple design a whole new chip? How much is borrowed from the A-series family?  How much is new design?  How much is Apple investing to achieve the desired functionality for Macs?  It is time to look at a T2 and find out what Apple created for their Intel-based Mac co-processor.

Package & hints of memory

The T2 under study came from a 2019 13” MacBook Air logic board.  The T2’s package has a decent footprint compared to the other ICs around it.  For comparison, the larger of the shiny dies to the right of the T2, between four mounts, is the Intel i5.  One can envision the T2 being a similar size, based on the package.  There is a “1847” date code on the package indicating late 2018 assembly.

2019 13” MacBook Air logic board

A teardown of the late 2018 MacBook Air simply listed the T2’s part number.  However, a teardown of a 2019 15” MacBook Pro indicated the T2 was “layered on a 1 GB Micron D9VLN LPDDR4 memory”.  Our package also included the “D9VLN” marking.  A decoder at Micron points to a 1GB LPDDR4.  The T2 and memory would likely be in a Package-On-Package (PoP) arrangement.

A second die was in fact found in the beaker after de-packaging.  The markings visible at top metal are Micron’s.  The inclusion of in-package DRAM is interesting, not to mention costly, for a companion IC or co-processor.  It is however not too surprising considering the T2 is derived from the A-series that has long had in-package DRAM.

Top metal die markings of second die in T2 package.

Die photo & “PUs”

It is time for the main event.  SEM analysis of several line pitches and 6T SRAM cell size confirmed the T2 is fabbed in a TSMC16 nm process.  This is the same node as the A10, so the latter will serve as a reference A-series processor against which the T2 can be compared.

T2 die photo with CPU and GPU annotations.

A10 die photo with original annotations.  Source: Chipworks

Visually, the CPU is the  first thing that jumps out at you.  It is the same design and layout as the A10.  Assuming the T2 was designed after the A10, the CPU was dropped in as a hard macro.  Remember it is a 4-core CPU!  There are two performance i.e. large Hurricane cores and two efficiency i.e. small Zephyr cores.  That is quite a bit power considering there is already an Intel i5 for the main system processor.

One can only imagine the conversation within Apple.  “Do you have any CPU’s ready to go?”  “Yup … there is a 4-core 17.4 mm2 design that is only a few months old on the shelf over there.” “Great, I’ll take one of those.” Well, maybe it was a bit more technical.

The GPU does not follow suit.  The A10’s 6-core GPU is organized as 3 blocks for the cores and a block of logic.  The T2’s GPU appears to be along the lower edge of the die.  Again, the cores are organized as 3 blocks.  We did not discern symmetry within these blocks, suggesting 3 cores.  The GPU logic is likely in a block just above the cores, where the hashed lines encircle a potential area for it.  Even if all 3 blocks within this area were GPU logic, it would be smaller than that identified for the A10.  There is more analysis needed here to confirm the GPU configuration, but there are suggestions that both the GPU’s logic and cores are smaller than those on the A10.

Additional block-level analysis is ongoing.  We see blocks that were used as-is, when compared to the A10, ones that received a new layout, and straight-up new design.

Early numbers

The T2 measures 9.6 mm by 10.8 mm, yielding a die size of 104 mm2.  It is not a small die!  The T2 is a serious processor.  This is roughly 80% of the A10’s 125 mm2.

As expected, the CPU has an area of approximately 17.4 mm2 on both dies.  This yields a higher % of the total die dedicated to the CPU in the T2.  The T2’s GPU is considerably smaller than the A10’s.  Each core comes in at 1.2 mm2 v. 5.3 mm2 for the cores of the A10.  Functionally, this makes sense as the T2 GPU should not be tasked near as much as the A10’s because it is not the primary GPU.  Again, there is already either Intel embedded graphics or a dedicated GPU on the logic board.

Pulling threads together

There is plenty more to extract from the reverse engineering, but this snippet provides a flavor of Apple’s thinking.  As a starting point, Apple looks to user functionality.  An ongoing question at Apple seems to be “What do we want the user to experience from an Apple product?”  Then they build it.  The T2 became Apple’s interpretation of this for Intel-based Macs, but remember prior to the T1 the Intel processors were flying solo, and Macs still worked.

The T2 leveraged design from the A-series processors as shown in the CPU.  It’s 4-core CPU is large, to say the least, and it is hard not to think it is overpowered for the T2.  That said, Apple would look at the cost of re-design v. the silicon cost associated with dropping in something that might be larger than is truly needed.  The latter was probably more enticing as the wafer starts for the T2 would be nowhere near those of the A10, or any A-series processor for that matter.  Besides, the extra horsepower will provide a better experience.

The T2 also consolidated stand-alone ICs within a Mac.  The storage or SSD controller is one example of this.  Apple bought Israeli-based Anobit in 2011.  The 2016 13” MacBook Pro (with Function Keys) included an Apple stand-alone storage controller (see slide 11).  The controller became a block on the T2.  Today, it would be a block on the M1.

Conclusion

We will continue to dig into the T2, focusing on the known block functionalities, it’s comparison with the A10 and looking forward.  Yes, the T2 and the A10 are both old designs, but the comparison liberates information about use of semiconductor design and the effort Apple invests to provide their desired user experience.

*This article is jointly authored by Lev Klibanov. Dr. Klibanov is an independent consultant in semiconductor process and related fields. Dr. Klibanov has focused on and has considerable experience in advanced CMOS logic, non-volatile memory, CMOS image sensors, advanced packaging, and MEMS technologies.  He has spent 20+ years working in reverse engineering, metrology, and fabrication.

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VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm

VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm
by Scotten Jones on 07-02-2021 at 6:00 am
Categories: Events, Semiconductor Services, TechInsights, TSMC
3 Comments

Figure 1

At the 2021 Symposium on VLSI Technology and Circuits in June a short course was held on “Advanced Process and Devices Technology Toward 2nm-CMOS and Emerging Memory”. In this article I will review the first two presentations covering leading edge logic devices. The two presentations are complementary and provide and excellent overview of the likely evolution of logic technology.

CMOS Device Technology for the Next Decade, Jin Cai, TSMC

Gate length (Lg) scaling of planar MOSFETs is limited to approximately 25nm because the single surface gate has poor control of sub surface leakage.

Adding more gates such as in a FinFET where the channel is constrained between three gates yields the ability to scale Lg to approximately 2.5 times the thickness of the channel. FinFETs have evolved from Intel’s initial 22nm process with highly sloped fin walls to todays more vertical walls and TSMC’s high mobility channel FinFET implemented for their 5nm process.

Taller fins increase the effective channel width (Weff), Weff = 2Fh + Fth, where Fh is the fin height and Fth is the fin thickness. Increasing Weff increases drive current for heavily loaded circuits but excessively tall fins waste active power. Straight and thin fins are good for short channel effects but Fw is limited by reduced mobility and increase threshold voltage variability. Implementing a high mobility channel (authors note, SiGe for the pFET fin) in their 5nm technology gave TSMC an ~18% improvement in drive current.

As devices scale down parasitic resistance and capacitance become a problem. Contacted Poly Pitch (CPP) determine standard cell widths (see figure 1) and is made up of Lg, Contact Width (Wc) and Spacer Thickness (Tsp), CPP = Lg + Wc + 2Tsp. Reducing Wc increases parasitic resistance unless process improvements are made to improve the contacts and reducing tsp increases parasitic capacitance unless slower dielectric constant spacers are used.

Figure 1. Standard Call Size.

 As the height of a standard cell is reduced the number of fins per device has to be reduced (fin depopulation), see figure 2.

Figure 2. Fin Depopulation.

Fin depopulation reduced cell size increasing logic density and provide higher speed and lower power, but it does reduce drive current.

Transitioning from FinFETs to stacked Horizontal Nanosheets (HNS) enable increased flexibility by varying the sheet width (see figure 3.) and the ability to increase Weff by stacking more sheets.

 Figure 3. Flexible Sheet Width.

Adding sheets adds to Weff, Wee = N*2(W+H), where N is the number of sheets, W is the sheet width and H is the sheet height (thickness). Ultimately the number of sheets is limited by the performance of the bottom sheet. The spacing between sheets reduces parasitic resistance and capacitance as it is reduced but must be big enough to get the gate metals and dielectric into the gap. There is a bottom parasitic mesa device under and HNS stack that can be control by implants or a dielectric layer.

In FinFET nFET electron mobility is higher than pFET hole mobility. In HNS the mobility is even more unbalanced with higher electron mobility and lower hole mobility. Hole mobility can be improved by cladding the channel with SiGe or using a Strain Relaxed Buffer but both techniques add process complexity.

Imec has introduced a concept called a Forksheet (FS) where a dielectric layer is put between the nFET and pFET reducing the n-p spacing resulting in a more compact standard cell, see figure 4.

Figure 4. Forksheet.

 Beyond a HNS with FS, there is the Complementary FET (CFET) that stacks the nFET and pFET eliminating the need for horizontal n-p spacing.

Figure 5. CFET.

CFET options include monolithic integration where both nFET and pFET devices are fabricated on the same wafer and sequential integration where the nFET and pFET are fabricated on separate wafers that are then bonded together, both options have multiple challenges that are still being worked on.

Beyond CFET the presenter touched on 3D integration with transistor integrated into the Back End Of Line (BEOL) interconnect. These options require low temperature transistors with polysilicon channels or oxide semiconductors presenting a variety of performance and integration challenges.

In the Front End Of Line (FEOL) options beyond CFETs are being explored such as high mobility materials, Tunnel FETs (TFET), Negative Capacitance FETs (NCFET), Cryogenic CMOS and low dimensional materials.

Low dimensional materials make take the form of nanotubes or 2D Materials, these materials offer even shorter Lg and lower power than HNS but are still in the early research phase. Low dimensional materials also fit into the HNS/CFET approach with the option to stack up many layers.

Nanosheet Device Architecture to Enable CMOS Scaling in 3nm and beyond: Nanosheet, Forksheet and CFET, Naoto Horiguchi, Imec.

This section of the course expanded on the HNS/FS/CFET options discussed in the previous section.

As FinFETs are being scaled to the limits, fins are getting taller, thinner and closer. Fin depopulation is reducing drive current and increasing variability, see figure 6.

Figure 6. FinFET scaling.

The state-of-the-art today is a 6-track cell with 2 fins per device. Moving to single fins and narrower n-p spacing will require new device architectures to drive performance, see figure 7.

Figure 7. 6-Track Cell

To continue CMOS scaling we need to transition from FinFET sot HNS to HNS with FS and then CFETs, see figure 8.

Figure 8. Nanosheet Architectures for CMOS Scaling.

Transitioning from FinFETs to HNS offer several advantages, great Weff, improved short channel effect which means shorter Lg and better design flexibility due to the ability to vary the sheet width, see figure 9.

Figure 9. FinFET to HNS.

The presenter went on to go into detail on HNS processing and some of the challenges and possible solutions. A HNS process is very similar to FinFET processing except for four main modules, see figure 10.

Figure 10. HNS Process Flow.

Although a HNS flow is similar to a FinFET flow the key modules that are different are difficult. The release etch and achieving multiple threshold voltages is particularly difficult. There was a lot of good information on the specifics of the process modules changes required for HNS that is beyond the scope of a review article like this. One thing that wasn’t explicitly discussed is that in order to scale a HNS process to a 5-track cell Buried Power Rails (BPR) are required and that is another difficult process module that is still being developed.

As seen in the previous presentation further scaling of HNS can be achieved by FS. Figure 11 presents a more detailed view of how a dielectric wall shrinks a HNS cell.

Figure 11. Horizontal Nanosheet/Forksheet Structure Comparison.

The FS process requires the insertion of a dielectric wall to decrease the n-p spacing, figure 12 illustrates the process flow.

Figure 12. Forksheet Process Flow.

Beyond FS, CFET offers zero horizontal n-p spacing by stacking devices. Figure 13. Illustrates the CFET concept.

Figure 13. CFET Concept.

CFETs are particularly interesting for SRAM scaling. SRAM scaling has slowed and is not keeping up with logic scaling. CFET offer the potential to return SRAM scaling to the historical trend, see figure 14.

Figure 14. SRAM Scaling with CFET.

As previously mentioned there are two approaches to CFET fabrication, monolithic and sequential. Figure 15 contrasts the two approaches with pluses and minuses for each.

Figure 15. CFET Fabrication Options.

Conclusion

This review presented some of the key points of the two presentations leading edge logic devices. This is just an overview of the excellent and more detailed information presented in the course. The course also covered interconnect, contacts, and metrology for logic, and emerging memory, 3D memory and DRAM. I highly recommend the short courses.

Also Read:

Is IBM’s 2nm Announcement Actually a 2nm Node?

Ireland – A Model for the US on Technology

How to Spend $100 Billion Dollars in Three Years

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 Semiconductor CapEx strong in 2021

 Semiconductor CapEx strong in 2021
by Bill Jewell on 06-23-2021 at 10:00 am
Categories: Semiconductor Intelligence, Semiconductor Services, TSMC
2 Comments

Semiconductor CAPEX spending versus change 2021

Semiconductor manufacturers are expanding capital spending in 2021 and beyond to help alleviate shortages. In addition, many governments around the world are proposing funding to support semiconductor manufacturing in their countries.

The United States Senate this month approved a bill which includes $52 billion to fund semiconductor research, design, and manufacturing. The bill has support in the U.S. House and from President Biden.

The Japan Ministry of Economy, Trade and Industry earlier this month announced a “national project” to support semiconductor manufacturing in Japan.

South Korea announced in May a plan to spend $450 billion over the next ten years on non-memory semiconductor manufacturing paid for by private business and government tax credits.

The European Union in May announced it is ready to commit “significant” funds to expand semiconductor manufacturing in Europe.

These government initiatives will help support investment by semiconductor manufacturers. SEMI’s latest fab forecast predicts the industry will break ground on 19 new high-volume semiconductor fabs in 2021 and 10 in 2022. Equipment spending on these fabs should exceed $140 billion. China and Taiwan will each account for 8 new fabs, with 6 in the Americas, 3 in Europe and the Mideast and 2 each in Japan and South Korea.

Semiconductor industry capital expenditures (CapEx) totaled $113 billion in 2020, according to IC Insights. Projections for 2021 growth range from 16% to 23%.

Three companies accounted for over 50% of semiconductor capital spending in 2020. Samsung, the largest spender in 2020 at $27.9 billion, is expected to keep spending flat in 2021. TSMC will have the largest increase, adding $12.8 billion from 2020 to reach $30 billion in 2021, a 74% increase. TSMC will account for over 60% of the total industry spending increase of $20.4 billion. Intel has stated it will increase spending from $14.3 billion in 2020 to $19.5 billion in 2021, up 37%. The 2021 projections were mostly made in April after first quarter earnings release. Many of these numbers will likely be revised upward over the course of 2021.

The semiconductor industry has traditionally experienced boom-bust cycles. Large investments are made to expand capacity during high demand periods. When demand growth slows or declines, over-capacity leads to declining revenue. This trend is illustrated in the graph below. Annual change in semiconductor capital expenditures is depicted by the green bars on the left axis scale. Annual change in the semiconductor market is shown by the blue line on the right axis scale. The red line labeled “CapEx Danger Line” indicates where an increase in CapEx over 40% leads to trouble for the semiconductor market.

Large increases in semiconductor capital spending are followed in one to two years by a decline (or significant growth deceleration) in the semiconductor market. When the semiconductor market grew 46% in 1984, CapEx increased 106%. This was followed by a 17% decline in the semiconductor market in 1985. In 1988 the semiconductor market grew 38% and CapEx grew 57%. Following this, the semiconductor market decelerated by 30 points to 8% growth in 1989. The next big growth period was in 1993 to 1995, peaking at in 1995 at 42% market growth and 75% CapEx growth. The next year the market declined 9%. An 8% market decline in 1998 was due to the Asian financial crisis.

The semiconductor market expanded by 37% in 2000 at the peak of the internet boom. This was accompanied by a 77% increase in CapEx. In 2001, the market had its largest decline in history at 32%. In 2004 a 28% market increase and 52% CapEx increase was followed by a 21-point deceleration to 7% growth in 2005. Semiconductor market declines in 2008 and 2009 were driven by the global financial crisis. Strong growth returned in 2010 with 32% market growth and 107% CapEx growth. The market decelerated by over 30 points in 2011 to almost zero growth followed by a 3% decline in 2012. In 2017 the market increased 22% and Capex increased 41%. 2017 growth was relatively modest compared to prior peak growth rates. However, two years later in 2019 the market declined by 12%.

There are numerous factors affecting the semiconductor market growth rate including the overall economy and demand for key electronics products. However, large increases in capacity have invariably led to overcapacity when demand slows. The overcapacity leads to semiconductor price declines, especially for commodity products such as memory. Inventories held by electronics manufacturers and distributors are cut. This overcapacity tends to occur following CapEx increases of over 40%. This is indicated by the red CapEx danger line in the graph.

With forecasts of 2021 CapEx growth in the range of 16% to 23%, the industry is nowhere close to the “danger line” of over 40% growth. Even if CapEx growth accelerates in the second half of 2021, it is not likely to exceed 30%. TMSC is comfortable with a 74% CapEx increase since it has numerous foundry customers clamoring for more capacity. Two other foundries, UMC and GlobalFoundries, each plan to at least double CapEx in 2021 versus 2020. Foundry company SMIC of China plans to cut CapEx 25% in 2021 primarily due to trade issues. The memory companies such as Samsung are cautious on CapEx after seeing a 33% decline in the memory market two years ago in 2019.

While the current situation does not portend excessive semiconductor capacity in the near term, it bears watching in the next couple of years. It remains to be seen how much of the current semiconductor shortage is due to short-term disruptions from the pandemic and how much is due to increasing demand for electronic equipment and increasing semiconductor content.

Also Read:

Supply Issues Limit 2021 Semiconductor Growth

Automakers to Blame for Semiconductor Shortage

Electronics Back Strongly in 2021

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Highlights of the TSMC Technology Symposium 2021 – Automotive

Highlights of the TSMC Technology Symposium 2021 – Automotive
by Tom Dillinger on 06-15-2021 at 6:00 am
Categories: Automotive, Events, Foundries, TSMC
1 Comment

automotive market growth v2

At the recent TSMC Technology Symposium, TSMC provided a detailed discussion of their development roadmaps.  Previous articles have reviewed the highlights of silicon process and packaging technologies.  The automotive platform received considerable emphasis at the Symposium – this article specifically focuses on the automotive-related announcements.

As illustrated below, the forecasts of semiconductor content in automotive designs show considerable and extended growth.

Advanced driver assistance systems (Level 4/5 autonomy) will experience high adoption in upcoming models, with extensive sensor integration, requiring significant increases in computational throughput for image processing and decision control.

TSMC described a number of process technology enhancements, ranging from high-voltage power management to microcontroller functionality to image sensors to (5G) wireless vehicle communication to advanced digital performance, all specifically for the “automotive grade” environment.

Review of Automotive Grades

The demanding and varied applications for the electronic control units and sensors in an automotive system necessitate specific definitions of environmental and reliability qualification specifications – in short, these are represented as different grades.  AEC-Q100 is an industry standard specification that defines the specific qualification procedures:

    • AEC-Q100 Grades
        • Grade 0: -40C to 150C  (automotive, under the hood)
        • Grade 1: -40C to 125C  (automotive)
        • Grade 2: -40C to 105C  (industrial)
        • Grade 3: -40C to 85C  (commercial)

BCD Technologies for Automotive

TSMC offers multiple families of BCD (Bipolar-CMOS-DMOS) technologies, in support of the different high-voltage domains within an automotive network, as illustrated below.

Continuing generational enhancements focus on reducing device on-resistance (Ron), to improve PMIC efficiency.

Embedded NVMs for automotive MCUs

Microcontrollers in automotive ECUs require embedded non-volatile memory blocks, for over-the-air (OTA) maintenance/feature updates.  As the complexity of automotive electronic systems grows, MCUs will trend to newer process nodes for better PPA, and will require dense, high-reliability eNVM technology.

Key aspects of the eNVM reliability are the endurance cycle and data retention performance.  The eNVM roadmap for the TSMC automotive platform is shown below.

At the N28 node, embedded flash memory is being qualified for Grade 0.  Beyond the N28 node, magnetoresistive random access memory (MRAM) technology will be displacing eFlash.  N22 MRAM is in high-volume production (Grade 1, 100K cycles, 10 years retention, and high-immunity to external magnetic field).  N16 MRAM will be (Grade 1) qualified in 4Q22.

N5A

To address the computational requirement of (Level 4/5) data processing, TSMC is extending the production N5 process node to Grade 2 automotive qualification in 2022.

This N5A platform offering involves extending the design enablement support to Grade 2, from PDK models to TSMC library IP to aging/EM reliability analyses.  Correspondingly, the TSMC OIP partners are working on extending their IP support to N5A, as well.

With regards to IP, the automotive platform is also required to demonstrate functional and electrical model quality plus safety features, through compliance with the ISO26262 standard, adhering to Automotive Safety Integrity Level (ASIL) specifications.

 

Clearly, the automotive platform is receiving significant R&D investment at TSMC, in anticipation of extended growth in the semiconductor MCU and sensor content in upcoming years.  Increasing ADAS adoption and sales of EVs are driving a broad set of technology requirements, from PMICs to 5G RF wireless to high-end digital computation.

For more info on TSMC’s automotive platform, please follow this link.

-chipguy

 

 

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Highlights of the TSMC Technology Symposium 2021 – Packaging

Highlights of the TSMC Technology Symposium 2021 – Packaging
by Tom Dillinger on 06-14-2021 at 6:00 am
Categories: Events, Foundries, TSMC
2 Comments

3D Fabric

The recent TSMC Technology Symposium provided several announcements relative to their advanced packaging offerings.

General

3DFabricTM

Last year, TSMC merged their 2.5D and 3D package offerings into a single, encompassing brand – 3DFabric.

2.5D package technology – CoWoS

The 2.5D packaging options are divided into the CoWoS and InFO families.

  • CoWoS-S

The “traditional” chip-on-wafer-on-substrate with silicon interposer for die-to-die redistribution layer (RDL) connectivity is celebrating its 10th year of high-volume manufacturing.

  • CoWoS-R

The CoWoS-R option replaces the (expensive) silicon interposer spanning the extent of the 2.5D die placement area with an organic substrate interposer.  The tradeoff for the CoWoS-R is the less aggressive line pitch for the RDL interconnects – e.g., 4um pitch on the organic, compared to sub-um pitch for CoWoS-S.

  • CoWoS-L

Between the silicon –S and organic –R interposer options, the TSMC CoWoS family includes a newer addition, with a “local” silicon bridge for (ultra-short reach) interconnect between adjacent die edges.  These silicon slivers are embedded in an organic substrate, providing both high density USR connections (with tight L/S pitch) and the interconnection and power distribution features of (thick) wires and planes on an organic substrate.

Note that CoWoS is designated as a “chip last” assembly flow, with die attached to the fabricated interposer.

  • 2.5D package technology – InFO

InFO utilizes (single or multiple) die on a carrier that are subsequently embedded in a reconstituted wafer of molding compound.  The RDL interconnect and dielectric layers are subsequently fabricated on the wafer, a “chip-first” process flow.  The single-die InFO provides a high-bump count option, with the RDL wires extending outward from the die area – i.e., a “fan-out” topology.  As illustrated below, the multi-die InFO technology options include:

    • InFO-PoP: “package-on-package”
    • InFO-oS: “InFO assembly-on-substrate”
  • 3D packaging technology – SoIC

The 3D packages are associated with the SoIC platform, which utilizes stacked die with direct pad bonding, in either face-to-face or face-to-back orientations – denoted as SoIC chip-on-wafer.  Through silicon vias (TSVs) provide connectivity through a die in the 3D stack.

The SoIC development roadmap is illustrated below – as an example, N7-on-N7 die configurations will be qualified in 4Q21.

New Packaging Technology Announcements

There were several key announcements at this year’s Symposium.

  • maximum package size and RDL enhancements

The demand for a larger number of 2.5D die integrated into a single package drives the need for RDL fabrication across a larger area, whether on an interposer or the reconstituted wafer.  TSMC has continued to extend the “stitching” of interconnects past the single exposure maximum reticle size. Similarly, there is a need for additional RDL layers (with aggressive wire pitch).

The roadmap for larger package sizes and RDL layers includes:

    • CoWoS-S: 3X reticle (qualified by YE’2021)
    • CoWoS-R: 45X reticle (3X in 2022), 4 RDL layers on the organic substrate (W/S: 2um/2um), in reliability qualification using an SoC + 2 HBM2 die stacks
    • CoWoS-L: test vehicle in reliability assessment at 1.5X reticle size, with 4 local interconnect bridges between 1 SoC and 4 HBM2 die stacks
    • InFO_oS: 5X reticle (51mm x 42mm, on a 110mm x 110mm package), 5 RDL layers (W/S: 2um/2um), currently in reliability assessment

The figure below illustrates a potential InFO_oS configuration, with logic die surrounded by I/O SerDes chiplets, in support of a high-speed/high-radix network switch.

    • InFO_B (bottom)

The InFO_PoP configuration shown above depicts an InFO assembly with a DRAM module attached on top, with vias between the DRAM and the RDL interconnect layers.

TSMC is altering this InFO_PoP offering, to enable the (LPDDR DRAM) package assembly to be completed at an external contract manufacturer/OSAT, an option denoted at InFO_B, as shown below.

Correspondingly, TSMC has extended the “Open Innovation Platform” to include 3DFabric partners qualified for InFO_B final assembly.  (Currently, the 3DFabric partner companies are:  Amkor Technology, ASE Group, Integrated Service Technology, and SK Hynix.)

    • CoWoS-S “standard architecture” (STAR)

A prevalent design implementation for CoWoS-S is the integration of a single SoC with multiple High-Bandwidth Memory (HBM) die stacks.  The data bus width between the logic die and the HBM2E (2nd generation) stacks is very large – i.e., 1024 bits.

The routing and signal integrity challenges to connect the HBM stacks to the SoC through the RDL are considerable.  TSMC is providing systems companies with several standard CoWoS-S design configurations to expedite engineering development and electrical analysis schedules.  The figure below illustrates some of the different CoWoS-S options, ranging from 2 to 6 HBM2E stacks.

TSMC anticipates a high adoption rate of these standard design implementations in 2021.

  • new TIM materials

A thermal interface material (TIM) thin film is commonly incorporated into an advanced package, to help reduce the total thermal resistance from the active die to the ambient environment.  (For very high power devices, there are commonly two TIM material layers applied – an internal layer between the die and package lid and one between the package and heat sink.)

Corresponding to the increased power dissipation of larger package configurations, the TSMC advanced packaging R&D team is pursuing new internal TIM material options, as depicted below.

  • advanced packaging (AP) manufacturing capacity expansion

In anticipation of increased adoption of the full complement of 3DFabric packaging, TSMC is investing significantly in expanding the advanced packaging (AP) manufacturing capacity, as illustrated below.

For more information on TSMC’s 3DFabric technology, please follow this link.

-chipguy

 

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Highlights of the TSMC Technology Symposium 2021 – Silicon Technology

Highlights of the TSMC Technology Symposium 2021 – Silicon Technology
by Tom Dillinger on 06-13-2021 at 6:00 am
Categories: Events, Foundries, TSMC

logic technology roadmap

Recently, TSMC held their annual Technology Symposium, providing an update on the silicon process technology and packaging roadmap.  This article will review the highlights of the silicon process developments and future release plans.

Subsequent articles will describe the packaging offerings and delve into technology development and qualification specifically for the automotive sector.  Several years ago, TSMC defined four “platforms” which would receive unique R&D investments to optimize specific technical offerings:  high performance computing (HPC); mobile; edge/IoT computing (ultra-low power/leakage); and, automotive.  The focus on process development for the automotive market was a prevalent theme at the Symposium, and will be covered in a separate article.

Parenthetically, these platforms remain the foundation of TSMC’s roadmap.  Yet, the mobile segment has evolved beyond (4G) smartphones to encompass a broader set of applications.  The emergence of the “digital data transformation” has led to increased demand for wireless communication options between edge devices and cloud/data center resources – e.g., WiFi6/6E, 5G/6G (industrial and metropolitan) networks.  As a result, TSMC is emphasizing their investment in RF process technology development, to address this expanding segment.

General

Here are some general highlights from the Symposium, followed by specific process technology announcements.

  • breadth of offerings

In 2020, TSMC extended their support to encompass 281 distinct process technologies, shipping 11,617 products to 510 customers.  As in previous years, TSMC proudly stated “we have never shut down a fab.”

  • capacity

Current capacity in 2020 exceeds 12M (12” equivalent) wafers, with expansion investments for both advanced (digital) and specialty process nodes.

  • capital equipment investment

TSMC plans to invest a total of US$100 billion over the next three years, including a US$30 billion capital expenditure this year, to support global customer needs.

TSMC’s global 2020 revenue was $47.78B – the $30B annual commit to fab expansion certainly would suggest an expectation of significant and extended semiconductor market growth, especially for the 7nm and 5nm process families.  For example, new tapeouts (NTOs) for the 7nm family will be up 60% in 2021.

  • US fab

TSMC has begun construction of a US fab in Phoenix, AZ – volume production of the N5 process will commence in 2024 (~20K wafers per month).

  • environmental initiatives

Fabs are demanding consumers of electricity, water, and (reactive) chemicals.  TSMC is focused on transitioning to 100% renewable energy sources by 2050 (25% by 2030).  Additionally, TSMC is investing in “zero waste” recycling and purification systems, returning used chemicals to “electronic grade” quality.

One cautionary note…  Our industry is famously cyclic, with amplified economic upticks and downturns.  The clear message from TSMC at the Symposium is that the accelerating adoption of semiconductors across all platforms — from data-intensive computation centers to wireless/mobile communications to automotive systems to low-power devices – will continue for the foreseeable future.

Process Technology Roadmap

  • N7/N7+/N6/N5/N4/N3

The figure below summarizes the advanced technology roadmap.

N7+ represents the introduction of EUV lithography to the baseline N7 process.  N5 has been in volume production since 2020.

N3 will remain a FinFET-based technology offering, with volume production starting in 2H2022.  Compared to N5, N3 will provide:

  • +10-15% performance (iso-power)
  • -25-30% power (iso-performance)
  • +70% logic density
  • +20% SRAM density
  • +10% analog density

TSMC foundation IP has commonly offered two standard cell libraries (of different track heights) to address the unique performance and logic density of the HPC and mobile segments.  For N3, the need for “full coverage” of the performance/power (and supply voltage domain) range has led to the introduction of a third standard cell library, as depicted below.

Design enablement for N3 is progressing toward v1.0 PDK status next quarter, with a broad set of IP qualified by 2Q/3Q 2022.

N4 is a unique “push” to the existing N5 production process.  An optical shrink is directly available, compatible with existing N5 designs.  Additionally, for new designs (or existing designs interested in pursuing a physical re-implementation), there are some available enhancements to current N5 design rules and an update to the standard cell libraries.

Similarly, N6 is an update to the 7nm family, with increasing adoption of EUV lithography (over N7+).  TSMC indicated, “N7 remains a key offering for the increasing number of 5G mobile and AI accelerator designs in 2021.”

  • N7HPC and N5HPC

An indication of the demanding performance requirements of the HPC platform is the customer interest in applying supply voltage “overdrive”, above the nominal process VDD limit. TSMC will be offering unique “N7HPC” (4Q21) and “N5HPC” (2Q22) process variants supporting overdrive, as illustrated below.

There will be a corresponding SRAM IP design release for these HPC technologies.  As expected, designers interested in this (single digit percentage improvement) performance option will need to address increased static leakage, BEOL reliability acceleration factors, and device aging failure mechanisms.  TSMC’s investment in the development and qualification of processes specifically optimized for individual platforms is noteworthy.  (The last HPC-specific process variant was at the 28nm node.)

  • RF technology

The market demand for WiFi6/6E and 5G (sub-6GHz and mmWave) wireless communications has led TSMC to increase focus on process optimizations for RF devices.  RF switches are also a key application area.  Low power wireless communication protocols, such as Bluetooth (with significant digital integration functionality) are a focus, as well.  Automotive radar imaging systems will no doubt experience growing demand.  The mmWave applications are summarized in the figure below.

The two key parameters typically used to describe RF technology performance are:

  • device Ft (“cutoff frequency”), where current gain = 1, inversely proportional to device channel length, L
  • device Fmax (“maximum oscillation frequency”), where power gain = 1, proportional to the square root of Ft, inversely proportional to the square root of Cgd and Rg

The TSMC RF technology roadmap is shown below, divided into different application segments.

  • N6RF

The N6RF process was highlighted at the Symposium – a device performance comparison to N16FFC-RF is shown below.

The N28HPC+RF and N16FFC-RC processes also recently received enhancements – for example, improvements in the parasitic gate resistance, Rg, were highlighted.  For low-noise amplifier (LNA) applications, TSMC is evolving their SOI offerings at 130nm and 40nm.

  • ULP/ULL Technologies

IoT and edge device applications are forecast to become more pervasive, demanding increasing computational throughput at very low power dissipation (ULP) combined with ultra-low leakage (ULL) static power dissipation for improved battery life.

TSMC has provided ULP process variants – i.e., operational functionality for IP at very low VDD supply voltage.  TSMC has also enabled ULL solutions, with devices/IP utilizing optimized threshold voltages.

An overview of the IoT (ULP/ULL) platform and process roadmap is given below.

The N12e process node was highlighted by TSMC, integrating an embedded non-volatile memory technology (MRAM or RRAM), with standard cell functionality down to 0.55V (using SVT devices; low Vt cells would enable lower VDD and active power at higher leakage).  Comparable focus has been made to reduce the Vmin and standby leakage current of N12e SRAM IP, as well.

Summary

At the Symposium, TSMC introduced several new process developments, with specific optimizations for HPC, IoT, and automotive platforms.  RF technology enhancements are also a focus, in support of rapid adoption of new wireless communications standards.  And, to be sure, although it didn’t receive much emphasis at the Symposium, there is a clear execution roadmap for the advanced mainstream process nodes – N7+, N5, and N3 – with additional continuing process improvements as reflected in the release of intermediate nodes N6 and N4.

For more information on TSMC’s digital technology roadmap, please follow this link.

-chipguy

 

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TSMC and the FinFET Era!

TSMC and the FinFET Era!
by Daniel Nenni on 06-09-2021 at 6:00 am
Categories: FinFET, Foundries, Intel Foundry, TSMC
11 Comments

Intel 22nm wafer

While there is a lot of excitement around the semiconductor shortage narrative and the fabs all being full, both 200mm and 300mm, there is one big plot hole and that is the FinFET era.

Intel ushered in the FinFET era only to lose FinFET dominance to the foundries shortly thereafter. In 2009 Intel brought out a 22nm FinFET wafer at the Intel Developers Conference and announced that chips would be available in the second half of 2011. True to their word, the first FinFET chip (code named Ivey Bridge) was officially announced in May of 2011. I remember being shocked that the details were not leaked prior to the announcement. Intel 22nm was truly a transformative process technology, absolutely.

Intel followed 22nm with 14nm which was late and yield challenged (double patterning FinFETs) which allowed the foundries to catch up (TSMC 16nm and Samsung 14nm). Samsung did a very nice job at 14nm and won quite a bit of business including a slice of the Apple iPhone pie.

TSMC took a different approach to FinFETs. After mastering double patterning on 20nm, TSMC added in FinFETs and called it 16nm. The density was less than Intel 14nm thus the name difference. Samsung 14nm was a similar density as TSMC 16nm but Samsung took the low road and pretended they were competitive with Intel. And that is why process nodes are now marketing terms, my opinion.

This all started what I call the Apple half step process development methodology. TSMC would release a new process version without fail for Apple every year. Prior to that processes were like fine wine, not to be uncorked until they were Moore’s Law ready. The half steps continued with TSMC adding partial EUV to a process already in HVM (7nm) then adding more EUV layers to 5nm and 3nm in a very controlled manner that allowed for superior yield learning and record breaking process ramps.

Intel 14nm is also when the “Intel versus TSMC” marketing battle started. Intel insisted that TSMC 20nm was a failure since it did not include FinFETs and foundries could not follow Intel since they were an IDM and TSMC was just a foundry with no in-house design experience.

As we now know, Intel was wrong on so many levels. First and foremost the foundry business is a services business with a massive partnership ecosystem which puts IDM foundries at a distinct disadvantage. It will be interesting to see how the Intel IDM 2.0 strategy pans out but most guesses are that it will fail harder than the previous attempt, but I digress.

Now let’s take a quick look at the TSMC FinFET process revenue steps starting with Q1 2019 and the Q1s that have followed:

In Q1 2019 FinFETs accounted for 42% of TSMC revenue. In Q1 2020 it was 54.5% In Q1 2021 it was a whopping 63% and you can expect this aggressive ramp to continue for three reasons:

(1) TSMC protects their FinFET processes recipes so there is no second sourcing.

(2) FinFETs mean more performance at less power and less power is critical given the environmental challenges the world is facing.

(3) TSMC is building massive amounts of FinFET capacity ($100B 3 year CAPEX) and with the current semiconductor shortage narrative that is a VERY big deal.

Bottom line: TSMC is pushing their 500+ customers hard into the FinFET era and that will again change the foundry landscape.

The trillion dollar question is: What will happen to the mature (non-FinFET) nodes in the not too distant future? And more importantly, what will happen to the foundries that did not make the jump to FinFETs?

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TSMC 2021 Technical Symposium Actions Speak Louder Than Words

TSMC 2021 Technical Symposium Actions Speak Louder Than Words
by Daniel Nenni on 06-01-2021 at 1:00 pm
Categories: Events, Foundries, TSMC
5 Comments

TSMC Symposium 2021

The TSMC Symposium kicked of today. I will share my general thoughts while Tom Dillinger will do deep dives on the technology side. The event started with a keynote by TSMC CEO CC Wei followed by technology presentations by the TSMC executive staff.

C.C. Wei introduced a new sound bite this year that really resonated with me and that was “actions speak louder than words”. TSMC has always reminded me that it is important to speak softly and carry a big stick. While this does not always get TSMC the best media coverage it works extremely well with customers, and of course is a key ingredient to the TSMC “World’s Trusted Foundry Partner” strategy. Transparency is another key ingredient and you will not find a more transparent foundry than TSMC.

Who else presents defect density numbers? Which is really where the rubber meets the road for ramping new process technologies. Let me remind you how lucky we are to have C.C. Wei leading TSMC. He is a brilliant technologist and a great leader which is a very unique combination. I fully expect the many CEO awards to come his way in the not too distant future, absolutely.

The keynote was followed by presentations from the executive staff.  Noticeably missing was Cliff Hou who is now Senior Vice President, Europe and Asia Sales. My guess is that direct customer experience is a stepping stone to something bigger for Cliff. That and gray hair.

Learn About:

  • TSMC’s smartphone, HPC, IoT, and automotive platform solutions
  • TSMC’s advanced technology progress on 7nm, 6nm, 5nm, 4nm, 3nm processes and beyond
  • TSMC’s specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more
  • TSMC’s advanced packaging technology advancement on InFO, CoWoS®, and SoIC and other exciting innovations
  • TSMC’s manufacturing excellence, capacity expansion plan, and green manufacturing achievement
  • TSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design

Y.J. Mii (Senior Vice President, Research & Development) discussed advanced logic technologies, technology innovation beyond 3nm, and advanced integration technologies.

Kevin Zhang (Senior Vice President, Business Development) discussed specialty technology development and offerings.

Y.J. Mii (Senior Vice President, Research & Development) discussed advanced technology value aggregation, design ecosystem readiness for N5-N4-N3, and RF design platform update, and 3DIC design ecosystem for system innovation.

Y.P. Chin (Senior Vice President, Operations) provided a manufacturing update with new capacity ramping and new fab status, advanced packaging and testing operation, and green manufacturing.

This was followed by more technical sessions on advanced technology for smartphone and HPC platforms, 3D fabric technology, advanced RF and analog technology, BCD technologies for PMIC, eNVM and automotive, and ultra-low power technology for IoT platforms.

There is a LOT of information to cover so let us know what you are most interested in and we will prioritize as appropriate. Or ask us questions and we can answer them directly.

Hopefully the other foundries will take this symposium to heart and talk more about actions and how they have helped customers, the environment, and the world of electronics in a transparent manner. Thank you for reading and there is plenty more to come.