Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Samsung ♥ GLOBALFOUNDRIES

Samsung ♥ GLOBALFOUNDRIES
by Daniel Nenni on 04-18-2014 at 11:00 pm

Had I not been briefed personally I may not have believed it. Samsung and GLOBALFOUNDRIES will work closely together on satisfying 14nm wafer demand while sharing Samsung’s FinFET secret sauce. This tells me two things: Samsung has more 14nm design wins than I had originally reported and the new GF CEO is serious about the… Read More


Intel Lost $1B in Mobile Last Quarter

Intel Lost $1B in Mobile Last Quarter
by Paul McLellan on 04-16-2014 at 8:00 am

Intel announced their quarterly results today. Revenue was $12.8B, up 1% from a year ago with operating income of $2.5B also up 1% from last year.

Since the future of the world is mobile and not desktop/laptop, the mobile results are the most interesting. Mobile sales fell 61% to $156M. This includes mobile products and anything … Read More


What, SD doesn’t have enough pins?

What, SD doesn’t have enough pins?
by Don Dingee on 04-16-2014 at 6:00 am

I was in a Twitter conversation over the weekend with some very smart people, and one of the discussion points was how slow and painful the formal standardization process can be. One suggestion was that IoT companies should “just do it”, creating specification-by-implementation. … Read More


U2U: Things You Might Not Know About TSMC

U2U: Things You Might Not Know About TSMC
by Paul McLellan on 04-10-2014 at 10:50 pm

At Mentor’s U2U this afternoon I attended a presentation on TSMC’s use of Calibre PERC (it is a programmable electrical rule checker) for qualification of IP in TSMC’s IP9000 program. I’ve written about this before here. Basically IP providers at N20SOC, N16FF, and below are required to use PERC to guarantee… Read More


FD-SOI, FinFET, 3D in Monterey

FD-SOI, FinFET, 3D in Monterey
by Paul McLellan on 04-09-2014 at 5:40 pm

Last night the IEEE Silicon Valley Chapter had a panel session that was in some ways a preview of some of what will be discussed at the Electronic Design Process Symposium in Monterey next Thursday and Friday. At EDPS Herb Reiter organized a session on FinFET, 3DIC and FD-SOI (sort of how many buzzwords can you get into one set of titles).… Read More


Who Wants to Live in Malta?

Who Wants to Live in Malta?
by Paul McLellan on 04-08-2014 at 11:49 am

Who wants to live in Malta? A beautiful island in the eastern Mediterranean with wonderful food…wait, that’s the wrong Malta. I’m talking about the one in upstate New York where GlobalFoundries have their big fab 8 and also their technology development center (also known as fab 8.1).

So why would you want to … Read More


What is Next for GLOBALFOUNDRIES?

What is Next for GLOBALFOUNDRIES?
by Daniel Nenni on 04-04-2014 at 8:30 am

In response to changing industry dynamics, AMD announced in October 2008 a new strategy to focus exclusively on the design phase of semiconductor product development. To achieve that strategy, AMD partnered with Advanced Technology Investment Company (ATIC) of Abu Dhabi to create a new joint venture company designed to become… Read More


FinFET Custom Design

FinFET Custom Design
by Paul McLellan on 04-02-2014 at 8:30 pm

At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor,… Read More


Imagine what all the DLP technology can do for you

Imagine what all the DLP technology can do for you
by Pawan Fangaria on 03-24-2014 at 7:00 pm

Light has become integral part of most of the electronic devices we use today in any sphere of influence; personal, entertainment, consumer, automotive, medical, security, and industrial and so on. It’s obvious; along with IoT (Internet-of-Things) devices, the devices to illuminate and display things will play a major role… Read More


Handel Jones on FD-SOI vs FinFET

Handel Jones on FD-SOI vs FinFET
by Paul McLellan on 03-20-2014 at 1:27 am

Handel Jones has a new white-paper out titled Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets. Handel has done an in-depth analysis of the wafer and die costs of the various approaches, bulk planar (what we have been doing up to now), FD-SOI and FinFET. The analysis… Read More