Intel Versus TSMC 14nm Processes

Intel has begun to release some details on their 14nm process. I thought it would be interesting to contrast what Intel has disclosed to TSMC’s 16nm process disclosure from last year’s IEDM (TSMC calls their 14nm process 16nm).

[TABLE] align=”center” border=”1″
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| style=”width: 141px” |
| style=”width: 163px” | Intel 14nm
| style=”width: 168px” | TSMC 16nm
| style=”width: 116px” | Ratio TSMC/Intel
|-
| style=”width: 141px” | Process target
| style=”width: 163px” | MPU
| style=”width: 168px” | SOC
| style=”width: 116px” |
|-
| style=”width: 141px” | Status
| style=”width: 163px” | Shipping
| style=”width: 168px” | Development
| style=”width: 116px” |
|-
| style=”width: 141px” | Process type
| style=”width: 163px” | FinFET on bulk
| style=”width: 168px” | FinFET on bulk
| style=”width: 116px” |
|-
| style=”width: 141px” | Gate
| style=”width: 163px” | Gate last HKMG
| style=”width: 168px” | Gate last HKMG
| style=”width: 116px” |
|-
| style=”width: 141px” | Fin pitch
| style=”width: 163px” | 42nm
| style=”width: 168px” | 48nm
| style=”width: 116px” | 1.14
|-
| style=”width: 141px” | Gate pitch
| style=”width: 163px” | 70nm
| style=”width: 168px” | 90nm
| style=”width: 116px” | 1.29
|-
| style=”width: 141px” | M1 pitch
| style=”width: 163px” | 52nm
| style=”width: 168px” | 64nm
| style=”width: 116px” | 1.23
|-
| style=”width: 141px” | SRAM cell size
| style=”width: 163px” | 0.0588um2
| style=”width: 168px” | 0.07um2
| style=”width: 116px” | 1.19
|-

There are both similarities and differences between the processes. Intel’s process is for MPUs and TSMC’s process is for SOCs. MPU processes are more targeted and require fewer options. A TSMC SOC process for example would typically have 2 or more gate oxide thicknesses with options for 4 or more Vts while Intel’s MPU processes are single gate oxide and at 22nm were 3Vts. On the other hand Intel is now shipping 14nm MPUs while TSMC will not be shipping SOCs on 16nm until mid-next year (although Intel will likely not ship their SOC version of 14nm until next year either). Intel’s disclosure also shows a significant density advantage over TSMC at almost 20% for SRAM cell size.

Also read:Who Will Lead at 10nm?

The preceding numbers are all based on TSMC’s IEDM paper from last December. TSMC is also known to have an FF and FF+ process. The FF+ process shows significant improvements in performance over FF. Is this due to a shrink or what performance enhancement is used to achieve this? It will also be interesting to see how Samsung’s 14nm process compares once we have critical dimensions for them. I would be very interested to hear from any Semiwiki readers who can provide additional information on the TSMC or Samsung processes.

A critical metric for both processes will be cost. Intel has already disclosed that 14nm produces a significant cost reduction per transistor versus 22nm (at least for MPUs). Various industry observers have published articles projecting increased cost per transistor for foundries at both 20nm and 16nm/14nm. Our modeling suggests TSMC will achieve a cost reduction at 20nm and may achieve a small cost reduction at 16nm as well.