TSMC Wafer Wars! Intel versus Apple!

The big fake news last week came from a report out of China stating that TSMC won a big Intel order for 3nm wafers. We have been talking about this for some time on SemiWiki so this is nothing new. Unfortunately, the article mentioned wafer and delivery date estimates that are unconfirmed and from what I know, completely out of line. From there the media created a frenzy pitting Intel against Apple and AMD in a war of wafers as a desperate attempt to get cheap clicks:

Intel locks down all remaining TSMC 3nm production capacity, boxing out AMD and Apple by John Loeffler Tech Radar

Intel Grabs Majority of TSMC’s 3nm Capacity by Hassan Mujtaba WCCftech

Intel Has Reportedly Cornered TSMC 3nm Chip Capacity by Paul Lilly HotHardWare

Apple secures majority of TSMC’s 3nm production capacity over Intel by Sean Gizmo China

And now we have wanna be influencers on Seeking Alpha and LinkedIn repeating this false narrative ad nauseum.

First let’s look at the TSMC/Apple backstory. Apple came to TSMC from Samsung at 20nm for the iPhone 6 which was the best phone of it’s time in my opinion. Apple first partnered with Samsung when founding the iPhone franchise but switched to TSMC after Samsung came out with their own line of smartphones that competed with their #1 foundry customer. A giant IP theft law suit followed which cemented Apple’s relationship with TSMC because as we all know, “TSMC is the trusted foundry and does not compete with customers”. As the story goes, Apple first approached Intel to make their SoCs but was rebuked, a decision that Intel greatly regrets.

The TSMC/Apple relationship disrupted the semiconductor manufacturing business by introducing what I call process technology half steps. Instead of following Moore’s law with a new process every two to three years TSMC released a new process version every year timed with the Apple iPhone Fall launch. In order to do that TSMC and Apple closely collaborate on a process technology optimized for the Apple SoCs which is frozen at the end of each year for high volume production in the second half.

The first half step was 20nm to 16nm. TSMC 20nm first introduced double patterning which was no small feat for chip designers. Next TSMC added FinFETs (another design challenge) to 20nm creating 16nm. TSMC uses the same fabs for the half steps which saves time and resources and promotes advanced yield learning for smoother process ramping. TSMC 16nm was further optimized for a 12nm version.

TSMC 10nm (N10) was the next process node which was followed by the N7 half step. Partial EUV was added to N7 (N7+) as another half step. N7+ was further optimized for N6.

TSMC N5 followed with more EUV and was further optimized for N4 which is what is in the iPhone products that will be launched next month (Apple’s version of N4).

TSMC N3 was officially launched at the TSMC Technology Symposium 2021 with even more EUV which will be in volume production starting in 2H2022 (Apple). As compared to N5, N3 will provide:

• +10-15% performance (iso-power)
• -25-30% power (iso-performance)
• +70% logic density
• +20% SRAM density
• +10% analog density

In the 10 years that TSMC and Apple have been working together an iPhone launch has never been missed and Apple has always been first to the new process technology. This collaborative half step process methodology is the reason TSMC and Apple have executed flawlessly. As a result, Apple is TSMC’s #1 customer and closest partner and I do not see that changing anytime soon, if ever, absolutely.

I first heard word of Intel having the TSMC N3 PDK in the first part of 2020 which was a bit of a surprise. Intel is a long time TSMC customer due to acquisitions but not for native Intel products. I confirmed it with multiple sources inside the ecosystem and started writing about it shortly thereafter.

What I was told later is that Bob Swan signed the N3 deal with TSMC due to the delays in Intel 10nm and 7nm to motivate Intel manufacturing to get those processes out as planned. TSMC then increased CAPEX to build the additional N3 capacity required to satisfy the Intel wafer agreement.

To be clear, wafer agreements are signed 2-3 years before the chip makes it into HVM and TSMC can build fabs faster than that so there will be no N3 shortages for anyone who signed a wafer agreement (apple, AMD, NVIDIA, QCOM, etc…). If they need more chips than what they signed up for, which happens, there may be shortages. This is how TSMC and the foundry business works. It’s all about the wafer agreements.

As an interesting side note, Pat Gelsinger and his new IDM 2.0 push has made the Intel/TSMC relationship all the more interesting. Pat insists that Intel will manufacture the majority of their products internally. I understand that 50.001% is technically a majority but that still seems low given the Intel TSMC N3 wafer agreement, the process delays Intel is currently experiencing, and the competitive pressures of AMD.

We covered the Intel Accelerated event last month and will be covering the Intel Architecture Day as well. Hopefully Intel’s new process and product initiatives are successful because competition is what keeps semiconductor technology moving forward and cost effective.

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