Changing RISC-V Verification Requirements, Standardization, InfrastructureA lively panel discussion about RISC-V and open-source…Read More
Semidynamics: A Single-Software-Stack, Configurable and Customizable RISC-V SolutionFounded with a vision to create transformative, customizable…Read More
Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early AdoptersThe demand for high-performance computing (HPC), data centers,…Read More
Arteris Empowering Advances in Inference AcceleratorsSystolic arrays, with their ability to highly parallelize…Read More
The Convergence of Functional with Safety, Security and PPA VerificationFormal For All! “Do I need a PhD…Read More
Intro
At DAC last week I visited the Synopsys demo suite to see what’s new with IC Validator.
Notes
Stelios Diamantidis, PMM
– In-design physical verification
– Sign-off reveals thousands of late stage DRC violations
– 28nm has 1.5K rules, 15K runset sizes
– Metal Fill changes timing
– The… Read More
Intro
Over the lunch hour on Tuesday at DAC I met with Emre Tuncer, VP – Product Engineering & Applications and heard about extraction and timing analysis.
Notes
GoldX – parasitic extractor. Fast extractor, recently announced, all new technology, early customer adoption. One customer deploying it in 40nm, soon to be 28nm.… Read More
Intro
For 22 years now Tanner EDAhas been in the business pf offering tools for AMS and MEMS designers. I learned what’s new at DAC on Tuesday morning.
Notes
Nicholas Williams – Director of Product Management
Tanner EDA front end: S-Edit integrates with Berkeley Fast Analog Simulator
W-Edit – is the waveform viewer
Who is … Read More
Intro
It’s all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what’s new for 2011.
Notes
What’s New in 2011 at Blue Pearl Software
New designer experience, ease of use. Brand new GUI.
Work with RTL to synthesis tools to get best timing… Read More
Dipesh Patel, VP Engineering, ARM Physical IP
Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)
Processor speeds: 1GHz to 1.5GHz
SOC Memory: 600MHz to 1.2 GHz
How power efficient?
How is the layout density?
Standard Cells: multi-channel, multi-vt (4) libraries
Memory Compilers:… Read More
Intro
The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.
Notes
Why 32/28nm
–Lower power, high integration requirements, mobile applications
What is Ready?
–IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)
–… Read More
The GlobalFoundries DRC+ platform is one of the most innovative DFM technologies and was well represented at #48DAC. In case you missed it, here is a reprint of a DRC+ overview from GFI just prior to #48DAC:
DRC (Design Rule Constraints) are the fundamental principles in constraining VLSI (Very Large Scale Integration) circuit… Read More
Intro
I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.
Notes
2010 – Announced a debugger
2011 ADDS Debugger – trace at the transistor level your design
– Signal tracing… Read More
Intro
John and Ralph from Magma gave me an update on QuickCap at DAC on Monday afternoon in their demo suite.
Notes
John Schritz – Sr AE
Ralph Iverson, Ph. D. (wrote QuickCap)
John Schritz
– Digital Signoff, extraction
– QCP: 2.5D RC for full ASIC designs
– QuickCAP NX: 3D field solver
– QCP:
Demo – 1.5 million… Read More
Hany El Hak – Product Marketing Manager
Frederik Iverson – AE
Scott Wetch – HSPICE Architect
HSPICE – 5 years ago convergence was not so good, while 95% of analog circuits today converge out of the box, no options are required.
Synopsys AMS Portfolio – wide range of tools
– Custom Designer: IC schematic and layout tools
–… Read More
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