Back in the Napoleonic era it was possible to manage a battle with very ad hoc methods. Sit on a horse on top of the highest hill and watch the battle unfold, send messengers out with instructions. By the First World War, never mind the second, that approach was hopelessly outdated and a much more structured way of managing a battle was… Read More
PLL Design Challenges for Integrated Circuit Designs
Nandu Bhagwan is CEO of GHz Circuits and has been designing PLL circuits used in ICs for the past 12 years. Mr. Bhagwan did a video interview with John Pierce of Cadence to talk about the challenges of PLL design.… Read More
Semiconductor IP Becomes A Critical Element in ASIC Design
Clearly one of the market trends proving troublesome in the traditional ASIC value chain is the lack of silicon correlated custom IP. And make no mistake, semiconductor IP is a critical decision since it drives both chip level and system level technology differentiation.
Under the traditional ASIC model, vendors had their own… Read More
Smartphones and Tablets Thirst for Bandwidth!
The explosive growth in portable devices over the past decade has left manufactures in a quandary over how to add memory to their products that meet several criteria:
- High capacity
- Low cost
- Low power
- High bandwidth
Magma FineSIM and MunEDA Cooperate
How do I know if an AMS block is tuned for the process and will perform and yield acceptably?… Read More
Semiconductors: A Decade of Invention… A World of Solutions
Please join IBM, Samsung Electronics, Co., Ltd., and GLOBALFOUNDRIES at the 2012 Common Platform Technology Forum. The forum will showcase the alliance’s technological progress and how joint collaboration and innovation is setting the direction for industry-leading solutions to enable next-generation products. … Read More
What Changed On My Transistor-Level Schematic?
Digital designers have used diff tools for years on their text-based HDL source code, but what about for the transistor-level IC designer, where is their diff tool for schematics or layout?… Read More
Multicore SoC Architecture Optimization
Once again with Synopsys and Arteris, the innovation is coming to solve an issue, faced by their potential customers: “In our research, we’ve found that almost half of project delays are caused by problems with the system architecture design and specification,” said Chris Rommel, vice president, embedded… Read More
DARPA looking for new base stations in new BYOD game
BYOD – bring your own device – has swept enterprises like a firestorm as CEOs wonder why they can’t use their shiny new iPad on the corporate network, and send their IT guys and gals off to make it happen. Under the right conditions and informed use, BYOD can be a productivity boom and not mess security and privacy up too badly for many … Read More
Words of AMS Wisdom from the Developer of Spectre, Spectre RF, Verilog-A, Verilog-AMS
Ken Kundert while at Cadence developed: Spectre, Spectre RF, Verilog-A and Verilog-AMS. About 6 years ago he and Henry Chang left Cadence and created a consulting company called The Designers Guide.
… Read More
More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay