DAC News – A New Era of Electronic Design Begins with Siemens EDA AIAI is the centerpiece of DAC this year.…Read More
Arteris at the 2025 Design Automation Conference #62DACKey Takeaways: Expanded Multi-Die Solution: Arteris showcases its…Read More
Secure-IC at the 2025 Design Automation Conference #62DACSecure-IC at DAC 2025: Building Trust into Tomorrow’s…Read More
The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embedded IP, a new IEEE P1687 standard is being defined by a broad coalition of IP vendors, IP users, major ATE companies, and all three major EDA vendors. This new standard, also called… Read More
Today I attended an Aldec webinar about ASIC and SoC prototyping using the new HES-7 Board. This prototyping board is based on the latest Virtex-7 FPGA chips from Xilinx.
You can view the recorded webinar here, which takes about 30 minutes (should be available in a few days). I first blogged about the HES-7 two months ago, ASIC Prototyping… Read More
Finding and debugging failures on integrated circuits has become increasingly difficult. Two sessions at ISTFA (International Symposium for Testing and Failure Analysis) on Thursday address the current best practices and research directions of diagnosis.
The first was a tutorial this morning by Mentor Graphics luminary… Read More
September WSTS data shows the 3Q 2012 semiconductor market increased 1.8% from 2Q 2012. The year 2012 semiconductor market will certainly show a decline. 4Q 2012 would need to grow 11% to result in positive growth for 2012. The outlook for key semiconductor companies points to a 4Q 2012 roughly flat with 3Q 2012. The table below shows… Read More
Until now, the integration and testing of IP blocks used in large SOCs has been a manual, time consuming design effort. A new standard called IEEE P1687 (or “IJTAG”) for IP plug-and-play integration is emerging to simplify these tasks. EDA tools are also emerging to support the new standard. Last week mentor announcedTessent IJTAG,… Read More
On October 1, Adesto Technologies announced that it had acquired Atmel’s DataFlash and Serial Flash business groups. At first sight, this seemed a rather counter intuitive move for one of the most aggressive (and visible) companies in the emerging memory field. The purchase raised many questions to those, not least the moderator… Read More
Any doubters of the importance of FPGA technology to the defense/aerospace industry should consider this: each Airbus A380 has over 1000 Microsemi FPGAs on board. That is a staggering figure, especially considering the FAA doesn’t trust FPGAs, or the code that goes into them.… Read More
I attended the Jasper User Group this week, at least the keynotes, the first by Kathryn Kranen the CEO of Jasper and the second by Bob Bentley of Intel.
Kathryn went over some history, going back to when the company was started (under the name Tempus Fugit) back in August 2002 with a single product for protocol verification. Now, since… Read More
Verification and AMS are top search terms on SemiWiki so clearly designers have a pressing need for fast and accurate verification of today’s mixed-signal SoCs that include massive digital blocks and precision analog/RF circuits. They need simulation performance to verify the mixed-signal functionality, and they need nanometer… Read More
We have shown in Semiwiki how strong Cadence position was in Verification IP (VIP) in a previous post focusing on Interface standards like SuperSpeed USB or PCI Express. But IP based functions are used everywhere in a SoC, not only to interface with the external world, and need to be verified, as well, like for AMBA based functions.… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot