ansys simworld semiconductors 800x100 1
WP_Term Object
(
    [term_id] => 178
    [name] => IP
    [slug] => ip
    [term_group] => 0
    [term_taxonomy_id] => 178
    [taxonomy] => category
    [description] => Semiconductor Intellectual Property
    [parent] => 0
    [count] => 1336
    [filter] => raw
    [cat_ID] => 178
    [category_count] => 1336
    [category_description] => Semiconductor Intellectual Property
    [cat_name] => IP
    [category_nicename] => ip
    [category_parent] => 0
)

Don’t miss this Panel! Platform & Subsystem IP: Trends and Realities

Don’t miss this Panel! Platform & Subsystem IP: Trends and Realities
by Eric Esteve on 12-03-2012 at 10:01 am

If you pass by Grenoble tomorrow (Tuesday 4th Dec.) and go to IP-SoC 2012, then you should attend this panel at 4pm in the Auditorium (you can’t miss it, it’s the larger room at the registration level).

If you are Designer, Architect, Project Manager, Marketing… working for a chip maker, please prepare questions! The topic is hot, but the success of the panel will come at least at 50% from questions from “customers”…

… the remaining 50% or less, we (Hal Barbour, CAST CEO, Peter Hirt, Director IP Procurement & Partnership at STM, Martin Lund, Senior VP, Research and Development, SoC Realization Group at Cadence, Jack Browne, Senior VP Marketing, Sonics, Bill Finch, CAST and I) are working on it, dropping some ideas to start the discussion!

Panel: Platform & Subsystem IP: Trends and Realities Since the mid-1990s when the concept of reusable IP cores first came into being, the proposal has always been that it was more economical to use and reuse IP than to always design chips from a clean start. It was also faster to market and more resource efficient. Many 3rd party IP companies came into being to supply IP that could be considered standard or that was so complex to design that doing the same function over and over was simply not practical. An example of the former would be a function like an Ethernet MAC and the latter would be something like a processor. Over the years this has proven to be a very successful practice for both chip designers and IP vendors and is one of the cornerstones of today’s business.

In the last few years with the exponential growth in gates available from the silicon suppliers, the pressure to use those gates to provide much more advanced functionality on a per chip basis has grown more and more intense. Functionality that is common in today’s smart phones, for example, was out of reach only a few short years ago. Getting to market in only a few months at price points that are astoundingly low is necessary for success. Many believe that this is the result of a shift to designing around reusable platforms and whole subsystems which gives entirely new meaning to the reusable IP concept. The idea of building a platform around which several different sets of functionality could be brought to market was viewed as something only the largest companies could engineer. Lately, there has been much hype about the 3rd party vendors expanding their offerings to at least the subsystem, if not the platform, level. The idea is to bring to the general market the advantages of higher levels of design reuse in effect recreating the success of IP cores at the next level. Is this really coming to pass or just industry hype and clever marketing? Do customers really want this and can the industry really deliver the kinds of flexibility customers will demand?

This panel attempts to examine the trend and discuss the realities of today’s platform IP market in addressing the requirements of both ASIC and FPGA designers.

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