Primarius 2B

Minitel Shuts Down

Minitel Shuts Down
by Paul McLellan on 07-05-2012 at 5:02 pm

When I first came to the US, one project that we had going on at VLSI Technology was an ASIC design being done by a French company called Telic. The chip would go into something called “Minitel” which the France Telecom (actually still the PTT since post and telecomunications had not yet been separated) planned to supply… Read More


IC Design at Novocell Semiconductor

IC Design at Novocell Semiconductor
by Daniel Payne on 07-05-2012 at 12:09 pm

In my circuit design past I did DRAM work at Intel, so I was interested in learning more about Novocell Semiconductor and their design of One Time Programmable (OTP) IP. Walter Novosell is the President/CTO of Novocell and talked with me by phone on Thursday.… Read More


Managing Differences with Schematic-Based IC Design

Managing Differences with Schematic-Based IC Design
by Daniel Payne on 07-02-2012 at 2:41 pm

At DAC in June I didn’t get a chance to visit ClioSoft for a product update so instead I read their white paper this week, “The Power of Visual Diff for Schematics & Layouts“. My background is transistor-level IC design so anything with schematics is familiar and interesting.

The Challenge
Hand-crafted … Read More


IC Test Sessions at SEMICON West 2012

IC Test Sessions at SEMICON West 2012
by Beth Martin on 07-02-2012 at 1:43 pm

SEMICON West is coming up this July 10-12 at the Moscone Center in San Francisco. It covers a broad swath of the microelectronics supply chain, but I was particularly interested in the test sessions. Here are two that I recommend.

The Value of Test for Semiconductor Yield Learning” on Tuesday, July 10, at 1:30p. The… Read More


Cadence’s NVM Express: fruit from subsystem IP based strategy

Cadence’s NVM Express: fruit from subsystem IP based strategy
by Eric Esteve on 07-02-2012 at 11:24 am

If we look at SoC design evolution, we have certainly successfully passed several steps: from transistor by transistor IC design using Calma up to design methodology based on the integration of 500K + gates IP like PCIe gen-3 Controller, one out of several dozens of IP integrated in today’ SoC for Set-Top-Box or Wireless Application… Read More


Crushed Blackberry

Crushed Blackberry
by Paul McLellan on 07-02-2012 at 12:00 am

I wasn’t going to write about the cell phone business again for some time. After all, this is a site about semiconductor and EDA primarily. But the cell-phone business in all its facets is a huge semiconductor consumer and continues to grow fast (despite my morbid focus on those companies that do anything but).

But Research… Read More


Synopsys IP Strategy 2012

Synopsys IP Strategy 2012
by Daniel Nenni on 07-01-2012 at 7:30 pm

Synopsys is the dominant player in the commercial EDA and semiconductor IP markets so it is always interesting to hear what John Koeter, Vice President of Marketing for IP, Services and System Level Solutions, has to say. John presented “The Role of IP in a Changing Landscape” at the SemiCO IMPACT Conference and I talked to him again… Read More


Dragon Boats and TSMC 20nm Update!

Dragon Boats and TSMC 20nm Update!
by Daniel Nenni on 07-01-2012 at 6:30 pm


My luck continues as I missed last week’s typhoon. Fortunately it did not disrupt the annual Dragon Boat Festival. More than just a Chinese tradition, dragon boat racing is an international sports event with teams from around the world coming to Taiwan every year. It is very exciting with the colorful dragon boats and the wild beating… Read More


The Scariest Graph I’ve Seen Recently

The Scariest Graph I’ve Seen Recently
by Paul McLellan on 07-01-2012 at 4:00 pm

Everyone knows Moore’s Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.

But I have always pointed out that this is not what drives… Read More