PowerArtist RTL Power Estimation Folds into KeysightBack in the late 1990s, Sente launched a…Read More
Intel Foundry Expands the 18A Platform with 18A-P and Demonstrates Long-Term Technology Leadership at VLSI 2026At the 2026 VLSI Symposium, Intel Foundry provided…Read More
GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneckAs semiconductor manufacturing pushes toward advanced nodes with…Read More
A tower-like heterogeneous packaging architecture for the AI era VEMC: The Vertical System…Read More
Akeana Collaborates with Samsung Electronics, Fast-Tracking RISC-V Customers and Ecosystem for Server and Agentic AI SiliconThe momentum behind RISC-V continues to accelerate as…Read More
Arasan recently adopted ClioSoft for data management (DM) for design and development of Arasan’s Silicon IP products. This morning I talked to Erik Peterson, Senior CAD and Verification Engineer AMS Design about their experiences bringing up ClioSoft.
Data management infrastructure is critical with engineering projects… Read More
The design and manufacture of MEMS is very different and in many ways more complex process than even the most advanced ICs. MEMS involve multiple degrees of freedom (i.e. the device to exhibit different characteristics under different physical state, motion or mechanics), making fabrication of MEMS extremely complex; and hence… Read More
I was tempted to call this piece “if you’re not using an FPGA, you’re doing it wrong,” but that didn’t quite capture the whole picture. Social memes aside, the FPGA as we know it is undergoing a serious transformation into a full blown SoC, and 2014 is the year that will usher in one of the biggest changes in the history of embedded design.… Read More
In the 1970’s we designed ICs first and when silicon came back then we measured the power and junction temperature. At that time there were no EDA simulation tools or models for full-chip power and temperature analysis. Fast forward to 2013 and we find that temperature and power are still demanding requirements for MPSoC … Read More
As smartphone and tablet makers desperately search for points of differentiation they will try to push the limits of performance on several fronts to extremes. The password pill and the display-cover display are two of the stranger extreme features on the way.
Extreme inter-connectivity is one of the more useful features that… Read More
We’ve become familiar with Imagination Technologies as a leading provider of IP for mobile GPUs, and within the last year the acquisition of the MIPS architecture has established them further in NPU and SoC circles. Their latest move targets an IP solution more in line with their heritage.
Imagination, way before becoming famous… Read More
One of the big questions on Intel’s foundry strategy is: Can they compete on wafer pricing? Fortunately there are now detailed reports that support what most of us fabless folks already know. The simple answer is no, Intel cannot compete with TSMC or Samsung on wafer pricing at 28nm, 20nm, and 14nm.
In fact, recent reports have shown… Read More
One of the challenges of physical design of a modern SoC is that of macro placement. Back when a design just had a few macros then the flooplanning could be handled largely manually. But modern SoCs suffer from a number of problems. A new white paper from Mentor covers Olympus-SOCs features to address these issues:
Jump into Xilinx Programmable Logic today! I wanted to encourage my dear readers if you have not tried using an Xilinx FPGA (Field Programmable Gate Array) or even CPLD (Complex Programmable Logic Device) then it is worth your time to begin your evaluation. Maybe you got one for Christmas? If not, it is easier than you think to start… Read More
Traditional logic testing relies on blasting pattern after pattern at the inputs, trying to exercise combinations to shake faults out of logic and hopefully have them manifested at an observable pin, be it a test point or a final output stage. It’s a remarkably inefficient process with a lot of randomness and luck involved.
Getting… Read More
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Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs