GlobalFoundries had several interesting things at the ARM TechCon last week. Firstly, GlobalFoundries won the best in show award in the chip design category recognizing the best-in-class technologies introduced since the last TechCon.
Earlier in the summer GlobalFoundries and ARM announced the ARM Cortex-A12 processor, for which GlobalFoundries was the foundry launch partner. The A12 is expected to be a very high volume processor since it is targeted at the low end of the smartphone market (which cannot afford a Cortex-A57 class processor). The low end of the smartphone market is expected to be the fastest growing going forward, the high end already being largely saturated.
Donar is the name GlobalFoundries use for the family of A12 test chips. They are based on Semper, which is an older family of A9 test chips taped out several times in 28nm and 20nm. They were created using a Cadence flow. In a joint presentation, GF and Cadence gave details on what was done. The design was a quad-core A12 and will tape-out imminently in GF’s 28nm-SLP process. It was the first experience for with the A12 for the entire project team of ARM, Cadence and GF.
The work was split up as follows. ARM developed the Cortex-A12, optimized POP components and the initial reference methodology. Cadence supplied the RTL to GDS2 implementation flow, methodology and tool support. GlobalFoundries supplied the Donar test chip design, 28nm-SLP MPW, full Cadence design flow enablement, development of a set of fast cache instances and design resources. The whole design was done on a very tight schedule between May and October.
Another interesting design that GF were showing in the exhibit hall is a 2.5D interposer-based design that was jointly created along with OpenSilicon. The design is called Avatar and consists of two ARM-based die in 28nm on a 65nm silicon interposer. This was a pipe-cleaner design to shake out problems with this sort of design, rather than anything that is expected to enter volume production.
Since there were no acceptable I/Os for this sort of design, OpenSilicon developed specialized die-to-die I/Os (which, of course, are now available for other designs). The problem with “normal” I/Os in this application is that the ESD requirements for full chip I/O is much too high, the drive requirement is too high since it is designed for a PCB trace, and the I/O needs to be small enough to fit under the microbump pitch.
The interposer has 4 front-side and 1 back-side layers of metal and through-silicon-vias (TSVs). The two die are assembled on the interposer. A lot of additional testing needs to be done on the die at wafer sort compared to a normal assembly because of what is called the “known good die” issue. If a faulty die slips through then not only does that bad die get discarded, an interposer and a second good die are also wasted.
2.5D interposer based designs allow different technologies to be mixed in the same design (although that was not done with Avatar). SoC with very wide memory, SoC with analog and high-speed interfaces, or even SoC and FPGA. As we move below 20nm it is hard to put analog on the same die and using a mature process that is optimized for analog design and then putting two or more die on an interposer is an attractive solution.Watch a video about GlobalFoundries 28nm here.