Taking a look at the coveted presentation slots at the CDNLive Conference next month you will see a presentation on Data Management for Mixed-Signal Designs by one of my favorite EDA companies, ClioSoft. Great software, great support, great people, and with customers that are willing to talk publicly about their tools and technology.… Read More





SPICE Circuit Simulation at STMicroelectronics
At the 2010 DACI moderated a panel session on SPICE and Fast SPICE circuit simulation, and one of the panelists was PierLuigi Dagliofrom STMicroelectronics. To get an update on SPICE circuit simulation at ST I read a PDF document at Mentor titled: Improving the Quality of SPICE Simulation Results with Eldo Premier at ST.
ST does … Read More
TSMC ♥ Cadence
In a shocking move TSMC now favors Cadence over Synopsys! Okay, not so shocking, especially after the Synopsys acquisitions of Magma, Ciranova, SpringSoft, and the resulting product consolidations. Not shocking to me at all since my day job is Strategic Foundry Relationships for emerging EDA, IP, and fabless companies.
Rick… Read More
SHIELDing the Android GPU developer in C
Repeat after me: SoCs are paperweights if they can’t be programmed. Succeeding with a new part today means supporting a robust developer program to attract and engage as many creatives as possible. NVIDIA has teamed up with Mentor Graphics in just such an adventure. If you read just the press release, you may have missed the real … Read More
Mentor Shines at DVCon
Mentor Graphics will be all over DVCon next week (February 25-28) at the DoubleTree hotel in San Jose.
In addition to attending all the panels, tutorials, posters, and the keynote, you can visit Mentor in booth 901 on the exhibit floor.
Here’s the lineup of Mentor-related events:… Read More
Why IP Must Be Defended
A few years ago I was having breakfast with Jim Hogan at our favorite place to meet in Los Gatos. I was CEO of Polyteda and Jim was Chairman so we always had plenty to talk about. This time, however, the talk had turned to protecting a company’s intellectual property (IP). Jim had brought up the topic in the context of the looming legal … Read More
ISSCC 2013: Circuit Design Using FinFETs!
One of the privilages of blogging for SemiWiki is invitations to the top conferences around the world including the International Solid-State Circuits Conference (ISSCC) in San Francisco this week. Amazing, this conference is older than I am:
ISSCC 2013 is the 60th Conference in an incredibly long-lasting series. Following… Read More
Aldec Delivers Leading Verification Methodologies!
For those of you who don’t know, Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification… Read More
Patenting in the (Resistive Memory) Material World
(with apologies to George Harrison) Two recent Blogs over at ReRAM-Forum.com have focused on the latest in the IP field, particularly as it affects resistive memory. A high level overview of who is patenting what suggests a healthy amount of R&D is going on in the field. But looking a little deeper suggests there is much overlap… Read More
Functional Check List in Verification
This article tries to bring out the advantages of having a functional check list. The objective is to make verification as robust as possible. Functional check list ensures the complete coverage of hardware block that is designed. This may to an extent help software developers. Creation of test plan with functional check list … Read More
RISC-V Virtualization and the Complexity of MMUs