Powering the Future: How Engineered Substrates and Material Innovation Drive the Semiconductor RevolutionEngineered substrate technology is driving an evolution within…Read More
CEO Interview: Dr. Andreas Kuehlmann of CycuityDr. Andreas Kuehlmann, Executive Chairman and CEO at…Read More
The Double-Edged Sword of AI Processors: Batch Sizes, Token Rates, and the Hardware Hurdles in Large Language Model ProcessingUnlike traditional software programming, AI software modeling represents…Read More
TRNG for Automotive achieves ISO 26262 and ISO/SAE 21434 complianceThe security of a device or system depends…Read More
Bug Hunting in Multi Core Processors. Innovation in VerificationWhat’s new in debugging multi-/many-core systems? Paul Cunningham…Read More
Incredibly exciting! Even my beautiful wife was impressed by the rainbow of colors it reflected. From left to right: 28nm, 20nm, and 14nm wafers. The 20nm and 14nm wafers are from the GLOBALFOUNDRIES NY fab, made in the USA! GF also announced another $3-4B CAPEX for 2013 to increase capacity of all three of their 300mm fabs (Singapore,… Read More
I was asked to make some predictions about the EDA, semiconductor and electronic systems markets for 2013. I decided that it would be more fun to make some plausible predictions, some of which will be right, rather than go for anodyne predictions (“Cadence will acquire a couple of startups”) which are uninformative,… Read More
Let’s play word association. I say “EDA”, you immediately think “Synopsys”. I say “IP” and although 15 years ago you may not, today, you think “Synopsys”. For nearly two decades, Synopsys has grown its IP business through both organic development and acquisition, with a clear focus on enabling designers to meet their time-to-market… Read More
Disclaimer: I’m a blogger and by definition I share my observations, opinions, and experiences. Journalists and Analysts on the other hand are held to a much higher legal standard which is why they cite undisclosed sources and use double speak to shield themselves legally. Why trust a SemiWiki blogger over a Journalist or an Analyst?… Read More
Sequential approaches to power reduction work well on logic implemented using standard cells. But part of every SoC, sometimes a very large part, is taken up with embedded memories for which alternative approaches are required. Not only do these memories occupy up to half of the area they also account for as much as 75% of the power… Read More
Satish Soman, chief solutions architect at Atrenta, was invited to give a presentation on Global Design Closure at the VLSI India conference in Pune at the start of this month. He talked about the need to close the gap between the typical SoC development methodology and what happens in reality.
SoCs are really put together in two … Read More
This morning I spoke with Mahesh Tirupattur, Executive VP of Analog Bits about IC design challenges and using EDA tools to create high performance, mixed-signal semiconductor IP.
The current methodology in design in most companies, and certainly many of the biggest, is that front end RTL design is done by one team with a limited set of front-end design tools. This is then eventually passed off to the physical design team who run all the scripts, do the “real” synthesis, place & route and timing… Read More
Who makes the decision and declare that a specific interface protocol is successful? Not me, as I can only consolidate market share data and some insight information coming from the industry. The end user, when going to a shop (real or virtual) and spend a significant part of his budget to buy an electronic product, selecting among… Read More
Sidense will be exhibiting at the Common Platform Technology Forum in Santa Clara, California on February 5, during which time they will be discussing their one-transistor, one-time programmable (1T-OTP) memory IP products. Based on their patented 1T-Fuse™ bit cell, Sidense antifuse-based 1T-OTP macros offer a secure, reliable,… Read More
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Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing