Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?Predictions in technology adoption often hinge on a…Read More
Webinar: Achieve Full Flow and Resource Management Visibility to Optimize Cost and Sustainability with InnovaThe lifecycle for complex chip design includes many…Read More
Crosstalk, 2kAmp power delivery, PAM4, and LPDDR5 analysis at DesignConHigh-speed digital (HSD) designers have long tested the…Read More
I have no idea if chicken was actually on the menu, but on December 12, Calibre RealTime picked up its thirdindustry award, this time the 2012 Elektra Award for Design Tools and Development Software from the European Electronics Industry. Calibre RealTime came out on top in a group full of prestigious finalists, including ByteSnap,… Read More
Anyone who has been around technology consortia or standards bodies will tell you that the timeline from inception to mainstream adoption of a new embedded technology is about 5 years, give or take a couple dream cycles. You can always tell the early stage, where very different concepts try to latch on to the same, simple term.
Such… Read More
There are two primary microprocessor companies in the world these days: Intel and ARM. Of course there are many others but Intel is dominant on the PC desktop (including Macs) and ARM is dominant in mobile (including tablets).
One of the keynotes at last month’s Jasper User Group (JUG, not the greatest of acronyms) was by Bob… Read More
Design For Manufacturing (DFM) is the art and science of making an IC design yield better in order to receive a higher ROI. Ian Smith, an AE from Mentor in the Calibre group presented a pertinent webinar, IP Scoring Using TSMC DFM Kits. I’ll provide an overview of what I learned at this webinar.… Read More
In an article published this week in microprocessor report and highlighted in Barron’s, Linley Gwennap makes the argument that Intel should stay the course and fix the PC instead of trying to offset its declines with sales into the Smartphone and Tablet space. He cites that lower PC sales growth was due to a dramatic slowdown in processor… Read More
We know by now that clock speeds aren’t everything when it comes to measuring the goodness of a processor. Performance has direct ties to pipeline and interconnect details, power factors into considerations of usability, and the unspoken terms of yield drive cost.
My curiosity kicked in when I looked at the recent press release… Read More
Short news came during last week-end and Linkedin was the most efficient media to learn that NVELO has been acquired. Probably very few people out of the SSD ecosystem knew about NVELO. Based in Santa Clara, the company was a spin off from Denali, privately owned and if you look at the top management, you will recognize a few name, like… Read More
Analog, mixed-signal, RF, and custom digital circuitry implemented in GHz nanometer CMOS introduce a new class of design and verification challenges that traditional transistor‑level simulators cannot adequately address. Berkeley Design Automation, Inc., (BDA) was founded in 2003 by Amit Mehrotra and Amit Narayan,… Read More
In 2012 FinFET is one of the most talked about MOS technologies of the year because traditional planar CMOS has slowed down on scaling below the 28nm node. To learn more about FinFET process modeling I attended a Synopsys webinar where Bari Biswas presented for about 42 minutes include a Q&A portion at the end.
Bari Biswas, Synopsys… Read More
Double patterning at 20nm is one of those big unavoidable changes that it is almost impossible to know too much about. Mentor’s David Abercrombie, DFM Program Manager for Calibre, has written a series of articles detailing the multifaceted impacts of double patterning on advanced node design and verification. There is… Read More
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Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?