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A Brief History of DSP…Not By Any of Us

A Brief History of DSP…Not By Any of Us
by Paul McLellan on 12-04-2013 at 11:35 am

I came across an interesting article by Will Strauss which is pretty much the history of DSP in communication chips. Having lived through the early part of the history while I was at VLSI Technology I found it especially interesting.

At VSLI, our first GSM (2G, i.e. digital not analog air interface) was a 5-chip chipset. The DSP functionality… Read More


SPICE Development Roadmap 2013!

SPICE Development Roadmap 2013!
by Daniel Nenni on 12-04-2013 at 11:00 am


The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, delivered its annual autumn compact modeling workshop on Sept. 20, 2013 as an integral part of the ESSDERC/ESSCIRC Conference in Bucharest (RO). The event received full sponsorship from leading industrial partners including Agilent… Read More


Intel Comes Clean on 14nm Yield!

Intel Comes Clean on 14nm Yield!
by Daniel Nenni on 12-04-2013 at 8:00 am

Hopefully this blog will result in a meaningful discussion on truth and transparency, and how Intel can do better in regards to both. Take a close look at the manufacturing slides presented by William Holt, Executive Vice President General Manager, Intel Technology and Manufacturing Group. You can see the slide deck HERE. Slide… Read More


Cadence & ARM Optimize Complex SoC Performance

Cadence & ARM Optimize Complex SoC Performance
by Pawan Fangaria on 12-03-2013 at 3:00 pm

Now a day, a SoC can be highly complex, having 100s of IPs performing various functionalities along with multi-core CPUs on it. Managing power, performance and area of the overall semiconductor design in the SoC becomes an extremely challenging task. Even if the IPs and various design blocks are highly optimized within themselves,… Read More


Webinar: Parasitic Debugging made easy!

Webinar: Parasitic Debugging made easy!
by Daniel Nenni on 12-03-2013 at 3:00 pm

We cordially invite you to attend this webinar and learn how to quickly debug post layout designs. Concept Engineering is a privately held company based in Freiburg, Germany. It was, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test … Read More


And the 2013 Mobile Winner is … Micron?

And the 2013 Mobile Winner is … Micron?
by Ed McKernan on 12-03-2013 at 9:00 am

To the surprise of nearly all observers and due to no extraordinary technological advancement, there is one true mobile winner of the past year and that is Micron, whose stock has soared in 2013 from $5 to $21. I know, you’re probably saying, “Micron, you can’t be serious.” Let’s run through the … Read More


Simplified Assertion Adoption with SystemVerilog 2012

Simplified Assertion Adoption with SystemVerilog 2012
by Daniel Payne on 12-02-2013 at 7:01 pm

SystemVerilog as an assertion language improved and simplified with the 2012 version compared to the 2005 version. I recently viewed a webinar on SystemVerilog 2012 by consultant Srinivasan Venkataramanan, who works at CVC Pvt. Ltd. There’s been a steep learning-curve for assertions in the past, and hopefully you’ll… Read More


Conquering errors in the hierarchy of FPGA IP

Conquering errors in the hierarchy of FPGA IP
by Don Dingee on 12-02-2013 at 10:00 am

FPGA design today involves not only millions of gates on the target device, but thousands of source files with RTL and constraints, often generated by multiple designers or third party IP providers. With modules organized in some logical way describing the design, designers brace themselves for synthesis and a possible avalanche… Read More


Because X doesn’t always mark the exact spot

Because X doesn’t always mark the exact spot
by Don Dingee on 11-30-2013 at 1:00 pm

Digital hardware has a habit of deciding – based on the bias and behavior of transistors – to drive outputs to a 0, or a 1, or if commanded a high-impedance Z state. SystemVerilog recognizes a fourth state: X, the “unknown” state a simulator has trouble inferring.

Simulators have a choice. Under X-optimism, they can convert the unknown… Read More


My iPhone 5s is having hot flashes!

My iPhone 5s is having hot flashes!
by Daniel Nenni on 11-29-2013 at 1:53 pm

It is bad enough my wife is “flashing” but now my phone is 100+ degrees too!?!?!? It seems that an application is getting stuck and the SoC is thrashing. Which application I do not know, you need to use the old process of elimination method to figure this one out. Doing a hard reboot (turning your phone off and on) is the quick fix, you can… Read More