The SoC designs of today are much more complex than ever in terms of number of clocks, IPs, levels of hierarchies, several modes of operations, different types of validations and checks for growing number of constraints at various stages in the design flow. As a semiconductor design evolves through several stages from RTL to layout,… Read More
CEO Interview with Dr. Maksym Plakhotnyuk of ATLANT 3DDr. Maksym Plakhotnyuk, is the CEO and Founder…Read More
Altair SimLab: Tackling 3D IC Multiphysics Challenges for Scalable ECAD ModelingThe semiconductor industry is rapidly moving beyond traditional…Read More
AI Booming is Fueling Interface IP 23.5% YoY GrowthAI explosion is clearly driving semi-industry since 2020.…Read More
4G shalt thou not count, neither count thou 2G
Five years from now, what will be the leading mobile connectivity standard? If you said 4G, please report to the brainwashing remediation center nearest you immediately. 3G is not only here to stay for the long haul, it’s growing – and will quickly become the preferred choice for M2M deployments.… Read More
U2U: Things You Might Not Know About TSMC
At Mentor’s U2U this afternoon I attended a presentation on TSMC’s use of Calibre PERC (it is a programmable electrical rule checker) for qualification of IP in TSMC’s IP9000 program. I’ve written about this before here. Basically IP providers at N20SOC, N16FF, and below are required to use PERC to guarantee… Read More
GSA 3DIC
At the GSA Silicon Summit this afternoon there was a discussion of 3D IC and 2.5D IC. The session was moderated by Javier DeLaCruz of eSilicon and the panelists were:
- Calvin Cheung of ASE (an OSAT)
- Gil Lvey of OptimalTest (a test house)
- Bob Patti of Tezzaron (semiconductor company specializing in TSV-based designs)
- Riko Radojcic
Advancements in Nanoscale Manufacturing
I’m at the GSA Silicon Summit today, at the computer history museum. The first panel session this morning was about future process technology. It was moderated by Joe Sawicki of Mentor with a panel consisting of Rob Aitken from ARM, Paul Farrar of G450C, Peter Huang of TSMC, John Kibarian of PDF Solutions and someone from Applied… Read More
Death to ‘content marketing’
If you ask me: Are you blogging for Semiwiki? The real answer could be:
No, I am just telling stories, but these are true stories! This idea is perfectly illustrated by this post that I found on:
http://www.pivotalpod.com/death-to-content-marketing/
And in particular this extract, as it is something that I could have written … Read More
Mentor’s New Enterprise Verification Platform
I spent the morning at Mentor where they announced their new enterprise verification platform. This was a general announcement but was attended by a lot of the international press who were over on a GlobalPress tour (the event that used to take up camp at Chaminade).
But first Wally Rhines spent 30 minutes giving a nice overview of… Read More
FD-SOI, FinFET, 3D in Monterey
Last night the IEEE Silicon Valley Chapter had a panel session that was in some ways a preview of some of what will be discussed at the Electronic Design Process Symposium in Monterey next Thursday and Friday. At EDPS Herb Reiter organized a session on FinFET, 3DIC and FD-SOI (sort of how many buzzwords can you get into one set of titles).… Read More
Addressing MCU Mixed Signal Design Challenges
The emerging market for IoT and wearable devices are designed with mixed-signal IP that includes: embedded CPU, flash, analogue and radio.EDA and IP companies have recently worked together to allow us to design an MCU with mixed-signal IP blocks more efficiently. This morning I attended a webinar with presenters from ARMand … Read More
How Qualcomm crushed the mobile roadmap
Qualcomm’s Snapdragon 810 announcement this week may seem like just another mondo-core SoC on a way-cool TSMC 20nm advanced process. Looking past the technology shows an understated genius in creating a roadmap – and why yours and most everyone else’s probably sucks.… Read More
TSMC N3 Process Technology Wiki