EDA rallied today for one of their own, without caring which company any of us worked for. We even got together in a ballroom in the San Jose Doubletree that I’m sure many of us have been in many times to endure way too many powerpoint slides at EDA conferences held there over the years. The instructions were to wear orange. At least… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural PivotIn 2003, legendary computer architect Michael J. Flynn…Read More
Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping SystemQualifying an AI-class RISC-V SoC demands proving that…Read More
DAC News – A New Era of Electronic Design Begins with Siemens EDA AIAI is the centerpiece of DAC this year.…Read More
Conquering the Next IoT Challenges with FPGA-Based Prototyping
The need for ever-connected devices is skyrocketing. As I fiddle with my myriad of electronic devices that seem to power my life, I usually end up wishing that all of them could be interconnected and controlled through the Internet. The truth is, only a handful of my devices are able to fulfill that wish, but the need is there and developers… Read More
Surprisingly Phablets Bucking the Trend
Amid a fiercely competitive market for computing devices, smartphones, tablets, and so on, a number of devices were created in this decade to invade into each other’s functionalities to either eat away other’s market share or retain their own. The key contenders were smartphones, Phablets, tablets and mini notebooks, whereas… Read More
Who Needs to Lead at the 14, 10 and 7nm nodes
IBM recently disclosed a working 7nm test chip generating a lot of excitement in the semiconductor industry and also in the mainstream media. In this article I wanted to explore the 14nm, 10nm and 7nm nodes, the status of the key competitors at each node and what it may mean for the companies.
Which High B/W Memory to Select after DDR4?
Once upon a time, RAM technology was the driver of the semiconductor process. DRAM products were the first to be designed on a newest technology node and DRAM was used as a process driver. It was 30 years ago and the most aggressive process nodes were ranging between 1um and 1.5 um (1 500 nm!). Then in the 1990 the Synchronous Dynamic … Read More
Tackling Layout Gradient Effects in 16 nm FinFET using Layout Automation
My first exposure to automating IC layout was back in the 1980’s at Intel where I coded a layout compiler to auto-generate about 6% of a graphics processor chip. The need to use automation for IC layout continues today, and with the advent of FinFET technology there are some new challenges like layout gradient effects that … Read More
The New York Times Announces 7nm
Everyone is somewhat focused on the march of process nodes. Moore’s Law, although I think that with the breach between technology and cost that may be changing. Moore’s Law was about the lowest cost way to get a given number of transistors manufactured. But now the lowest cost and the highest density are diverging. … Read More
After Five Years, 28nm Future Remains Bright!
Five years ago TSMC started 28nm mass production and it went on to become one of the most versatile and successful process technologies in history. The first wave was triggered by an unprecedented demand for application processors from smartphone and tablet vendors. Today it’s widely assumed that 28nm demand will continue growing… Read More
Updates for Effective Collaboration
Managing any design data management system requires a policy on how often users should be submitting their changes to the central repository. If users commit frequently with less local testing then other users will more likely see errors. If commits are done less often, but with better testing, then other users are protected from… Read More
Power Management Gets Tricky in IP Driven World
Today, an SoC can have multiple instances of an IP and also instances of many different IPs from different vendors. Every instance of an IP can work in a separate mode and requires a dedicated power arrangement which may only be formalized at the implementation stage. The power intent, if specified earlier, will need to be re-generated… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot