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Semiconductor Expert Forum

Podcast EP237: The Expanded Use of Functional Test Patterns for Manufacturing with Robert Ruiz

Podcast EP237: The Expanded Use of Functional Test Patterns for Manufacturing with Robert Ruiz
by Daniel Nenni on 07-26-2024 at 10:00 am
Categories: EDA, Synopsys

Dan is joined by Robert Ruiz, a product management director responsible for strategy and business growth of several verification products at Synopsys. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including Synopsys, Novas… Read More

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CEO Interview: Dr. Babak Taheri of Silvaco

CEO Interview: Dr. Babak Taheri of Silvaco
by Daniel Nenni on 07-26-2024 at 6:00 am
Categories: CEO Interviews, EDA, Silvaco

Babak Taheri Headshot

Babak A. Taheri, Ph.D., has served as Chief Executive Officer and member of the Silvaco board of directors from August 2019 to September 2021 and from November 2021 to present. From October 2018 to August 2019, Dr. Taheri served as our Chief Technology Officer and Executive Vice President of Products.

Tell us about your company?
… Read More
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Empowering AI, Hyperscale and Data Center Connectivity with PAM4 SerDes Technology

Empowering AI, Hyperscale and Data Center Connectivity with PAM4 SerDes Technology
by Kalar Rajendiran on 07-25-2024 at 10:00 am
Categories: AI, Cadence, EDA, IP

High Speed PAM4 SerDes Use Scenarios

The rapid expansion of data-intensive applications, such as artificial intelligence (AI), high-performance computing (HPC), and 5G, necessitates connectivity solutions capable of handling massive amounts of data with high efficiency and reliability. The advent of 224G/112G Serializer/Deserializer (SerDes) technology,… Read More

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CEO Interview: Dr. Pierre-Yves Lesaicherre of Finwave

CEO Interview: Dr. Pierre-Yves Lesaicherre of Finwave
by Daniel Nenni on 07-25-2024 at 10:00 am
Categories: CEO Interviews

Dr. Lesaicherre holds an MBA with a focus on International Business and Strategy from INSEAD, and has an MS degree and a PhD degree in Material Science from the Grenoble Institute of Technology (Grenoble INP).  He is a Board Leadership Fellow, Governance Fellow and Director Certified for NACD (National Association of Corporate… Read More

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Samtec Simplifies Complex Interconnect Design with Solution Blocks

Samtec Simplifies Complex Interconnect Design with Solution Blocks
by Mike Gianfagna on 07-25-2024 at 6:00 am
Categories: Samtec, Semiconductor Services

Samtec Simplifies Complex Interconnect Design with Solution Blocks

The development of cost effective, high-performance silicon to silicon interconnect at the system level can be a vexing problem. So many choices, which one will work best? Ease of use and customer support are woven into the DNA of Samtec. Almost four years ago I explored the company’s focus on putting the customer first here. Fast-forward… Read More

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Perforce IP and Design Data Management #61DAC

Perforce IP and Design Data Management #61DAC
by Daniel Payne on 07-24-2024 at 10:00 am
Categories: EDA, Events, Perforce

Helix IPLM, Helix Core min

I recall first blogging about Helix IPLM (formerly Methodics IPLM) at DAC in 2012, then Perforce acquired the company in July 2020, so I stopped by the Perforce booth this year at DAC to get an update from Martin Hall, Principal Solutions Engineer at Perforce. Martin’s background includes working at Dassault Systemes, Synchronicity,… Read More

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IROC Introduces an Upgraded Solution for Soft Error Analysis and Mitigation #61DAC

IROC Introduces an Upgraded Solution for Soft Error Analysis and Mitigation #61DAC
by Mike Gianfagna on 07-24-2024 at 6:00 am
Categories: EDA, Events, IROC Technologies

DAC Roundup – IROC Introduces an Upgraded Solution for Soft Error Analysis and Mitigation

#61DAC Is the place to go for the latest ideas, technology and products for semiconductor design and manufacturing. Between the exhibit floor and the technical program, you can get a vast education on almost any topic. In this post, I will focus on a unique company and a new version of a unique solution. IROC Technologies specializes… Read More

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Cadence® Janus™ Network-on-Chip (NoC)

Cadence® Janus™ Network-on-Chip (NoC)
by Kalar Rajendiran on 07-23-2024 at 10:00 am
Categories: Cadence, EDA, IP

Design Flow when using Janus NoC

A Network-on-Chip (NoC) IP addresses the challenges of interconnect complexity in SoCs by significantly reducing wiring congestion and providing a scalable architecture. It allows for efficient communication among numerous initiators and targets with minimal latency and high speed. A NoC facilitates design changes, enabling… Read More

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A Joint Solution Toward SoC Design “Exploration and Integration” released by Defacto #61DAC

A Joint Solution Toward SoC Design “Exploration and Integration” released by Defacto #61DAC
by Daniel Nenni on 07-23-2024 at 6:00 am
Categories: Defacto Technologies, EDA, Events

flow ip explorer soc compiler (1)

When I was at DAC last month, I had the chance to talk with Chouki Aktouf and Bastien Gratréaux from Defacto and they told me about a new innovative solution to generate Arm-based System-on-Chips. I heard that this solution has now been released.

Defacto and Arm developed a joint SoC design flow to help Arm users cover all needed automation—from… Read More

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TSMC Foundry 2.0 and Intel IDM 2.0

TSMC Foundry 2.0 and Intel IDM 2.0
by Daniel Nenni on 07-22-2024 at 10:00 am
Categories: 3D IC, Foundries, TSMC
7 Comments

TSMC 2Q2024 Investor Call

When Intel entered the foundry business with IDM 2.0 I was impressed. Yes, Intel had tried the foundry business before but this time they changed the face of the company with IDM 2.0 and went “all-in” so to speak. The progress has been impressive and today I think Intel is well positioned to capture the NOT TSMC business by providing… Read More