SILVACO 051525 Webinar 800x100 v2

SPIE Advanced Lithography 2018 – ASML Update on EUV

SPIE Advanced Lithography 2018 – ASML Update on EUV
by Scotten Jones on 04-09-2018 at 7:00 am

At the SPIE Advanced Lithography Conference in February ASML gave an update on their EUV systems, in this blog I will provide a summary of what they presented. I have also written about my impressions on EUV for the overall conference here.… Read More


NVIDIA GTC 2018 Then There Were Three

NVIDIA GTC 2018 Then There Were Three
by Roger C. Lanctot on 04-08-2018 at 8:00 am

If there was a central takeaway to Nvidia’s GTC event last week in San Jose it was this: autonomous vehicles are already operating or at least testing in virtual every corner of the planet including companies such as Tier IV and ZMP in Japan, and Pony.ai and Baidu in China. But two U.S. companies standout globally for the growing… Read More


The Good the Bad and Tesla and Uber

The Good the Bad and Tesla and Uber
by Roger C. Lanctot on 04-08-2018 at 7:00 am

In “Willy Wonka and the Chocolate Factory” circa 1971, Gene Wilder plays a vaguely misanthropic Willy Wonka who leads the young winners of his golden wrapper contest on a tour of the seven deadly sins within his candy factory and labs. (Who can forget Augustus Gloop?) At one point, Mike Teavee, a television-obsessed… Read More


EDA CEO Outlook 2018

EDA CEO Outlook 2018
by Daniel Nenni on 04-06-2018 at 12:00 pm

The EDA CEO outlook took an interesting turn last night but before I get into that I will offer a few comments about the start of the show. I attend this event every year for the content but also for the networking. It isn’t everyday you get to hang out with semiconductor industry elite and have candid conversations over food and drinks.… Read More


The 4th Way Beyond Simulation, FPGA Synthesis, and Emulation

The 4th Way Beyond Simulation, FPGA Synthesis, and Emulation
by Camille Kokozaki on 04-06-2018 at 7:00 am

As verification continues to be a key ingredient in successful design implementation, new approaches have been tried to balance cost, time to results and comprehensive analysis in designs that require large patterns in some application like Image Processing. Simulation environments are well proven, and designers tend to … Read More


Stress and Aging

Stress and Aging
by Bernard Murphy on 04-05-2018 at 12:00 pm

These failings aren’t just a cross we humans bear; they’re also a concern for chips, particularly in electrical over-stress (EOS) and aging of the circuitry. Such concerns are not new, but they are taking on new urgency given the high reliability and long lifetime expectations we have for safety-critical components in cars and… Read More


Mentor Leads Emulation Innovation

Mentor Leads Emulation Innovation
by Daniel Nenni on 04-05-2018 at 8:00 am

Publishing eBooks on FPGA Prototyping and Emulation really was an eye opener for me as a long time EDA and IP professional. Both markets are considered EDA in the traditional sense but they are very much in the systems business with a lot of IP. Both markets are also growing very rapidly and operate side-by-side with complimentary… Read More


A New Problem for High-Performance Mobile

A New Problem for High-Performance Mobile
by Bernard Murphy on 04-04-2018 at 7:00 am

About 6 months ago, ANSYS was approached by a couple of leading mobile platform vendors/suppliers with a challenging problem. These companies were hitting target 2.5GHz performance goals on their (N10 or N7) application processors, but getting about 10% lower yield than expected, which they attributed to performance failures.… Read More


Safety Critical Applications Require Onboard Aging Monitoring

Safety Critical Applications Require Onboard Aging Monitoring
by Tom Simon on 04-04-2018 at 6:00 am

When it comes to safety, ISO 26262 is the spec that comes to mind for many people. However, there are layers of specifications that enable the level of safety required for automotive and other systems that need high reliability. For any application requiring safety, test is a critical element. A key spec for SOC test is IEEE 1500, … Read More


Combining IP and Product Lifecycle Tools

Combining IP and Product Lifecycle Tools
by Daniel Payne on 04-03-2018 at 12:00 pm

No single EDA company provides all of the tools needed to define requirements, design exploration, track IP, simulate, manage and verify a complex SoC system, so it makes sense that EDA vendors and point tool companies have tools that work together to achieve all of these difficult tasks. Systems design has been around for decades… Read More