TSMC’s 2026 AZ Exclusive Experience Day: Bridging Careers and Semiconductor InnovationIn February of 2026, Taiwan Semiconductor Manufacturing Company…Read More
DAC – The Chips to Systems Conference 2026The Design Automation Chips to Systems Conference is…Read More
Taming Advanced Node Clock Network Challenges: JitterClock jitter rarely fails in obvious ways. In…Read More
Synopsys and AMD Honored for Generative and Agentic AI Vision, Leadership, and ImpactSynopsys and AMD were recently selected by the…Read More
The Foundry Model Is Morphing — AgainWhen Morris Chang left Texas Instruments in 1983 to found TSMC, he was…Read More
SMARTDV is one of the biggest small EDA companies in the industry today in regards to products, customers and number of licenses in use, absolutely. They have a portfolio of more than 600 Design & Verification Solutions, everything from Design & Verification IP to Formal Verification IP, Post-Silicon Verification IP… Read More
Presto Engineering recently held a webinar discussing vision chip technology – what a vision chip is, what are the applications and how can you optimize its use. Samer Ismail, a design engineer at Presto Engineering with deep domain expertise in vision chip technology was the presenter. Samer takes you on a very informative … Read More
Summary
A novel spin-transfer torque magnetoresistive memory (STT-MRAM) IP offering provides an attractive alternative for demanding high-performance embedded applications.
Introduction
There is a strong need for embedded non-volatile memory IP across a wide range of applications, as depicted in the figure below.
The… Read More
For years, the lords of Lyft and Uber have declaimed their intention to vanquish car ownership and displace public transportation. It really was as simple and as blunt as that. For sure there would be collateral damage including rental car companies and taxi operators and millions of under-compensated drivers – but the bottom
As most of you know DVCon 2020 was our first conference to be cut short by the Pandemic. SemiWiki bloggers Bernard Murphy, Mike Gianfagna, and I were there with full schedules but at the last minute it was called off. It really was an eerie feeling, the emptiness of it all.
The rest of our EDA live events followed suit and went virtual … Read More
In this first part of a 2-part blog series, we look at defining worst case conditions, focusing specifically on device power.
With great power, comes great responsibility…
With each new technology node especially FinFET, the dynamic conditions within a chip are changing and becoming more complex in terms of process speeds, thermal… Read More
As if engineers did not have enough difficulty just getting everything right so that their designs are implemented functionally correct, the demands of lowering power consumption require changes that can affect functionality and verification. Techniques such as power gating, clock gating, mixed supply voltage, voltage … Read More
The Information tells us that General Motors’ Cruise Automation self-driving car unit has acquired automotive radar maker Astyx. The move can be seen as a simple defensive move to preserve access to valuable radar technology along the path to realizing Cruise’s vision of a robotaxi infused future.
There are a variety
Cadence vManager™ Verification Management provides what the company describes as metric-driven signoff. Anyone who has been through the tapeout process for a complex SoC knows the perils of verification sign-off. How much of the chip has been verified? What’s left to do? Will all be ready when the tapeout deadline arrives? … Read More
Value chains can be very robust and seemingly unbreakable – until they’re not. One we’ve taken for granted for many years is the chain for electronics systems in cars. The auto OEM, e.g. Toyota, gets electronics module from a Tier-1 supplier such as Denso. They, in turn, build their modules using chips from a semiconductor chip maker… Read More
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The Risk of Not Optimizing Clock Power